ADuC7023BCBZ62I-R7 datasheet(67/96 Pages) AD

67 / 96 page

Data Sheet

ADuC7023

| Page 67 of 96

Table 74. I2CxFSTA MMR Bit Designations

Bit

Name

Description

15 to 10

Reserved bits.

I2CFMTX

This bit is set to 1 to flush the master

Tx FIFO.

I2CFSTX

This bit is set to 1 to flush the slave Tx

FIFO.

7 to 6

I2CMRXSTA

I2C master receive FIFO status bits.

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = 1 byte in FIFO.

[11] = FIFO full.

5 to 4

I2CMTXSTA

I2C master transmit FIFO status bits.

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = 1 byte in FIFO.

[11] = FIFO full.

3 to 2

I2CSRXSTA

I2C slave receive FIFO status bits.

[00] = FIFO empty

[01] = byte written to FIFO

[10] = 1 byte in FIFO

[11] = FIFO full

1 to 0

I2CSTXSTA

I2C slave transmit FIFO status bits.

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = 1 byte in FIFO.

[11] = FIFO full.

PROGRAMMABLE LOGIC ARRAY (PLA)

Every ADuC7023 integrates a fully programmable logic array

(PLA) consisting of sixteen PLA elements.

Each PLA element contains a two-input look-up table that can

be configured to generate any logic output function based on

two inputs and a flip-flop. This is represented in Figure 39.

LOOK-UP

TABLE

Figure 39. PLA Element

In total, 20 GPIO pins are available on the ADuC7023 for the

PLA. These include 11 input pins and nine output pins, which

need to be configured in the GPxCON register as PLA pins before

using the PLA.

The PLA is configured via a set of user MMRs. The output(s) of

the PLA can be routed to the internal interrupt system, to the

CONVSTART signal of the ADC, to an MMR, or to any of the

eight PLA output pins.

Table 75. Element Input/Output

PLA Block 0

PLA Block 1

Element

Input

Output

Element

Input

Output

P0.4

P0.7

P0.0

P0.2

P0.5

P1.0

P0.1

P0.3

P0.6

P1.1

P2.4

P2.51

P1.2

P1.4

P1.3

P1.5

P1.6

P2.11

P1.7

P2.2

P2.0

P2.3

Internal pins only. Read via GPxDAT register.

PLA MMRs Interface

The PLA peripheral interface consists of the 22 MMRs

described in the following sections.

PLAELMx Registers

PLAELMx are Element 0 to Element 15 control registers. They

configure the input and output mux of each element, select the

function in the look-up table, and bypass/use the flip-flop (see

Table 77).

Table 76. PLAELMx Registers

Name

Address

Default Value

Access

PLAELM0

0xFFFF0B00

0x0000

R/W

PLAELM1

0xFFFF0B04

0x0000

R/W

PLAELM2

0xFFFF0B08

0x0000

R/W

PLAELM3

0xFFFF0B0C

0x0000

R/W

PLAELM4

0xFFFF0B10

0x0000

R/W

PLAELM5

0xFFFF0B14

0x0000

R/W

PLAELM6

0xFFFF0B18

0x0000

R/W

PLAELM7

0xFFFF0B1C

0x0000

R/W

PLAELM8

0xFFFF0B20

0x0000

R/W

PLAELM9

0xFFFF0B24

0x0000

R/W

PLAELM10

0xFFFF0B28

0x0000

R/W

PLAELM11

0xFFFF0B2C

0x0000

R/W

PLAELM12

0xFFFF0B30

0x0000

R/W

PLAELM13

0xFFFF0B34

0x0000

R/W

PLAELM14

0xFFFF0B38

0x0000

R/W

PLAELM15

0xFFFF0B3C

0x0000

R/W

Rev. E

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