ADuC7023BCBZ62I-R7 datasheet(61/96 Pages) AD

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Data Sheet

ADuC7023

| Page 61 of 96

I2C Master Status Registers, I2CxMSTA

Name:

I2C0MSTA , I2C1MSTA

Address:

0xFFFF0804, 0xFFFF0904

Default value:

0x0000, 0x0000

Access:

Read

Function:

These 16-bit MMRs are the I2C status registers in master mode.

Table 66. I2CxMSTA MMR Bit Designations

Bit

Name

Description

15 to 11

Reserved. These bits are reserved.

I2CBBUSY

I2C bus busy status bit.

This bit is set to 1 when a start condition is detected on the I2C bus.

This bit is cleared when a stop condition is detected on the bus.

I2CMRxFO

Master Rx FIFO overflow.

This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.

This bit is cleared in all other conditions.

I2CMTC

I2C transmission complete status bit.

This bit is set to 1 when a transmission is complete between the master and the slave with which it was

communicating. If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

This bit clears this interrupt source.

I2CMNA

I2C master no acknowledge data bit.

This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write

transfer. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

I2CMBUSY

I2C master busy status bit.

This bit is set to 1 when the master is busy processing a transaction.

This bit is cleared if the master is ready or if another master device has control of the bus.

I2CAL

I2C arbitration lost status bit.

This bit is set to 1 when the I2C master has lost in trying to gain control of the I2C bus. If the I2CALENI bit in

I2C1MCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

I2CMNA

I2C master no acknowledge address bit.

This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If

the I2CNACKENI bit in I2C1MCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

I2CMRXQ

I2C master receive request bit.

This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2C1MCON is set, an interrupt is

generated.

This bit is cleared in all other conditions.

I2CMTXQ

I2C master transmit request bit.

This bit becomes high if the Tx FIFO is empty or only contains one byte and the master has transmitted an

address and write. If the I2CMTENI bit in I2C1MCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

1 to 0

I2CMTFSTA

I2C master Tx FIFO status bits.

00 = I2C master Tx FIFO empty.

01 = Reserved.

10 = 1 byte in master Tx FIFO.

11 = I2C master Tx FIFO full.

Rev. E

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