ADuC7023BCBZ62I-R7 datasheet(65/96 Pages) AD

65 / 96 page

Data Sheet

ADuC7023

| Page 65 of 96

Table 73. I2CxSSTA MMR Bit Designations

Bit

Name

Description

Reserved bit.

I2CSTA

This bit is set to 1 if: A start condition followed by a matching address is detected. It is also set if a start

byte (0x01) is received. If general calls are enabled and a general call code of (0x00) is received.

This bit is cleared on receiving a stop condition.

I2CREPS

This bit is set to 1 if a repeated start condition is detected.

This bit is cleared on receiving a stop condition.

12 to 11

I2CID[1:0]

I2C address matching register. These bits indicate which I2CxIDx register matches the received address.

[00] = received address matches I2CxID0.

[01] = received address matches I2CxID1.

[10] = received address matches I2CxID2.

[11] = received address matches I2CxID3.

I2CSS

I2C stop condition after start detected bit.

This bit is set to 1 when a stop condition is detected after a previous start and matching address.

When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated.

This bit is cleared by reading this register.

9 to 8

I2CGCID[1:0]

I2C general call ID bits.

[00] = no general call received.

[01] = general call reset and program address.

[10] = general program address.

[11] = general call matching alternative ID.

These bits are not cleared by a general call reset command.

These bits are cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON.

I2CGC

I2C general call status bit.

This bit is set to 1 if the slave receives a general call command of any type. If the command received is a

reset command, then all registers return to their default state. If the command received is a hardware

general call, the Rx FIFO holds the second byte of the command, and this can be compared with the

I2CxALT register.

This bit is cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON.

I2CSBUSY

I2C slave busy status bit.

This bit is set to 1 when the slave receives a start condition.

This bit is cleared by hardware if the received address does not match any of the I2CxIDx registers, the

slave device receives a stop condition or if a repeated start address does not match any of the I2CxIDx

registers.

I2CSNA

I2C slave no acknowledge data bit.

This bit is set to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted

under the following conditions: if no acknowledge is returned because there is no data in the Tx FIFO or if

the I2CNACKEN bit is set in the I2CxSCON register.

This bit is cleared in all other conditions.

I2CSRxFO

Slave Rx FIFO overflow.

This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.

This bit is cleared in all other conditions.

I2CSRXQ

I2C slave receive request bit.

This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur if the

I2CSRXENI bit in I2CxSCON is set.

The Rx FIFO must be read or flushed to clear this bit.

I2CSTXQ

I2C slave transmit request bit.

This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in

I2CxSCON is = 0, , this bit goes high just after the negative edge of SCL during the read bit transmission. If

the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the read

bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCON is set.

This bit is cleared in all other conditions.

Rev. E

ADuC7023BCBZ62I-R7 датащи(PDF) 65 Page - Analog Devices

ADuC7023BCBZ62I-R7 датащи(HTML) 65 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

датащи скачать

ссылки URL