ADuC7023BCBZ62I-R7 datasheet(63/96 Pages) AD

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Data Sheet

ADuC7023

| Page 63 of 96

I2C Address 1 Registers, I2CxADR1

Name:

I2C0ADR1, I2C1ADR1

Address:

0xFFFF081C , 0xFFFF091C

Default value: 0x00

Access:

Read/write

Function:

These 8-bit MMRs are used in 10-bit

addressing mode only. These registers contain

the least significant byte of the address.

Table 70. I2CxADR1 MMR in 10-Bit Address Mode

Bit

Name

Description

7 to 0

I2CLADR

These bits contain ADDR[7:0] in 10-bit

address mode.

I2C Master Clock Control Register, I2CxDIV

Name:

I2C0DIV, I2C1DIV

Address:

0xFFFF0824, 0xFFFF0924

Default value: 0x1F1F

Access:

Read/write

Function:

These MMRs control the frequency of the I2C

clock generated by the master on to the SCL

pin. For further details, see the I2C initial section.

Table 71. I2CxDIV MMR

Bit

Name

Description

15 to 8

DIVH

These bits control the duration of the high

period of SCL.

7 to 0

DIVL

These bits control the duration of the low

period of SCL.

I2C Slave Registers

I2C Slave Control Registers, I2CxSCON

Name:

I2C0SCON, I2C1SCON

Address:

0xFFFF0828, 0xFFFF0928

Default value: 0x0000

Access:

Read/write

Function:

These 16-bit MMRs configure the I2C

peripheral in slave mode.

Table 72. I2CxSCON MMR Bit Designations

Bit

Name

Description

15 to 11

Reserved bits.

I2CSTXENI

Slave transmit interrupt enable bit.

This bit is set to enable an interrupt after a slave transmits a byte.

This bit clears this interrupt source.

I2CSRXENI

Slave receive interrupt enable bit.

This bit is set to enable an interrupt after the slave receives data.

This bit clears this interrupt source.

I2CSSENI

I2C stop condition detected interrupt enable bit

This bit is set to enable an interrupt on detecting a stop condition on the I2C bus.

This bit clears this interrupt source.

I2CNACKEN

I2C no acknowledge enable bit.

This bit is set to no acknowledge the next byte in the transmission sequence.

This bit is cleared to let the hardware control the acknowledge/no acknowledge sequence.

I2CSSEN

I2C slave SCL stretch enable bit.

This bit is set to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low

until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.

This bit is cleared to disable clock stretching.

I2CSETEN

I2C early transmit interrupt enable bit.

This bit is set to enable a transmit request interrupt just after the positive edge of SCL during the read bit

transmission.

This bit is cleared to enable a transmit request interrupt just after the negative edge of SCL during the read bit

transmission.

Rev. E

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