ADuC7023BCBZ62I-R7 datasheet(77/96 Pages) AD

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Data Sheet

ADuC7023

| Page 77 of 96

IRQEN Register

Name:

IRQEN

Address:

0xFFFF0008

Default value:

0x00000000

Access:

Read/write

Function:

IRQEN provides the value of the current

enable mask. When each bit is set to 1, the

source request is enabled to create an IRQ

exception. When each bit is set to 0, the

source request is disabled or masked, which

does not create an IRQ exception.

To clear an already enabled interrupt source,

users must set the appropriate bit in the

IRQCLR register. Clearing an interrupt

IRQEN bit does not disable this interrupt.

IRQCLR Register

Name:

IRQCLR

Address:

0xFFFF000C

Default value:

0x00000000

Access:

Write

Function:

IRQCLR (write-only register) clears the

IRQEN register to mask an interrupt source.

Each bit set to 1 clears the corresponding bit

in the IRQEN register without affecting the

remaining bits. The pair of registers, IRQEN

and IRQCLR, independently manipulate the

enable mask without requiring an atomic

read-modify-write.

FAST INTERRUPT REQUEST (FIQ)

The fast interrupt request (FIQ) is the exception signal to enter

the FIQ mode of the processor. It is provided to service data

transfer or communication channel tasks with low latency. The

FIQ interface is identical to the IRQ interface and provides the

second level interrupt (highest priority). Four 32-bit registers

are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.

Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ

signal to the core and to Bit 0 of both the FIQ and IRQ registers

(FIQ source).

The logic for FIQEN and FIQCLR does not allow an interrupt

source to be enabled in both IRQ and FIQ masks. A bit set to 1

in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise,

a bit set to 1 in IRQEN clears, as a side effect, the same bit in

FIQEN. An interrupt source can be disabled in both IRQEN

and FIQEN masks.

FIQSIG

FIQSIG reflects the status of the different FIQ sources. If a

peripheral generates an FIQ signal the corresponding bit in

the FIQSIG is set, otherwise it is cleared. The FIQSIG bits are

cleared when the interrupt in the particular peripheral is cleared.

All FIQ sources can be masked in the FIQEN MMR. FIQSIG is

read only.

FIQSIG Register

Name:

FIQSIG

Address:

0xFFFF0104

Default value: 0x00000000

Access:

Read only

FIQEN

FIQEN provides the value of the current enable mask. When a bit is

set to 1, the corresponding source request is enabled to create an

FIQ exception. When a bit is set to 0, the corresponding source

request is disabled or masked which does not create an FIQ

exception. The FIQEN register cannot be used to disable an

interrupt.

FIQEN Register

Name:

FIQEN

Address:

0xFFFF0108

Default value: 0x00000000

Access:

Read/write

FIQCLR

FIQCLR is a write-only register that allows the FIQEN register

to clear in order to mask an interrupt source. Each bit that is set

to 1 clears the corresponding bit in the FIQEN register without

affecting the remaining bits. The pair of registers, FIQEN and

FIQCLR, allows independent manipulation of the enable mask

without requiring an atomic read-modify-write.

This register should only be used to disable an interrupt source

when in the interrupt sources interrupt service routine or if the

peripheral is temporarily disabled by its own control register.

This register should not be used to disable an IRQ source if that

IRQ source has an interrupt pending or could have an interrupt

pending.

FIQCLR Register

Name:

FIQCLR

Address:

0xFFFF010C

Default value:

0x00000000

Access:

Write only

Rev. E

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