ADuC7023BCBZ62I-R7 datasheet(38/96 Pages) AD

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ADuC7023

Data Sheet

| Page 38 of 96

SECURITY

The 62 kB of Flash/EE memory available to the user can be read

and write protected.

Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 34) protects

the 62 kB from being read through JTAG programming mode.

The other 31 bits of this register protect writing to the flash

memory. Each bit protects four pages, that is, 2 kB. Write

protection is activated for all types of access.

Three Levels of Protection

Protection can be set and removed by writing directly into

FEEHIDE MMR. This protection does not remain after reset.

Protection can be set by writing into FEEPRO MMR. It only

takes effect after a save protection command (0x0C) and a reset.

The FEEPRO MMR is protected by a key to avoid direct access.

The key is saved once and must be entered again to modify

FEEPRO. A mass erase sets the key back to 0xFFFF but also

erases all the user code.

Flash can be permanently protected by using the FEEPRO

MMR and a particular value of key: 0xDEADDEAD. Entering

the key again to modify the FEEPRO register is not allowed.

Sequence to Write the Key

1. Write the bit in FEEPRO corresponding to the page to be

protected.

2. Enable key protection by setting Bit 6 of FEEMOD (Bit 5

must equal 0).

3. Write a 32-bit key in FEEADR, FEEDAT.

4. Run the write key command 0x0C in FEECON; wait for

the read to be successful by monitoring FEESTA.

5. Reset the part.

To remove or modify the protection, the same sequence is used

with a modified value of FEEPRO. If the key chosen is the value

0xDEAD, the memory protection cannot be removed. Only a mass

erase unprotects the part, but it also erases all user code.

The sequence to write the key is illustrated in the following

example (this protects writing Page 4 to Page 7 of the Flash):

FEEPRO=0xFFFFFFFD;

//Protect Page 4 to

Page 7

FEEMOD=0x48;

//Write key enable

FEEADR=0x1234;

//16 bit key value

FEEDAT=0x5678;

//16 bit key value

FEECON= 0x0C;

//Write key command

The same sequence should be followed to

protect the part permanently with

FEEADR =

0xDEAD and FEEDAT = 0xDEAD.

FLASH/EE CONTROL INTERFACE

Serial and JTAG programming use the Flash/EE control interface,

which includes the eight MMRs outlined in this section.

FEESTA Register

Name:

FEESTA

Address:

0xFFFFF800

Default value: 0x20

Access:

Read

Function:

FEESTA is a read-only register that reflects the

status of the flash control interface as

described in Table 31.

Table 31. FEESTA MMR Bit Designations

Bit

Description

7 to 6

Reserved.

Flash interrupt status bit.

This bit is set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit

in the FEEMOD register is set.

This bit is cleared when reading FEESTA register.

Flash/EE controller busy.

This bit is set automatically when the controller is busy.

This bit is cleared automatically when the controller is not busy.

Command fail.

This bit is set automatically when a command is not completed.

This bit is cleared automatically when reading FEESTA register.

Command pass.

This bit is set by the MicroConverter when a command is completed.

This bit is cleared automatically when reading the FEESTA register.

Rev. E

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