ADuC7023BCBZ62I-R7 datasheet(72/96 Pages) AD

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ADuC7023

Data Sheet

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Table 85. PWMCON1 MMR Bit Designations

Bit

Name

Description

SYNC

Enables PWM synchronization.

Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low

transition on the P2.2/SYNC pin.

Cleared by the user to ignore transitions on the P2.2/SYNC pin.

Reserved

Set to 0 by the user.

PWM3INV

Set to 1 by the user to invert PWM3.

Cleared by the user to use PWM3 in normal mode.

PWM1INV

Set to 1 by the user to invert PWM1.

Cleared by the user to use PWM1 in normal mode.

PWMTRIP

Set to 1 by the user to enable PWM trip interrupt. When the PWM trip input (Pin P1.5/PWMTRIPINPUT) is low, the

PWMEN bit is cleared and an interrupt is generated.

Cleared by the user to disable the PWMTRIP interrupt.

ENA

If HOFF = 0 and HMODE = 1. Note that, if not in H-bridge mode, this bit has no effect.

Set to 1 by the user to enable PWM outputs.

Cleared by the user to disable PWM outputs.

If HOFF = 1 and HMODE = 1, see Table 86.

8 to 6

PWMCP[2:0]

PWM clock prescaler bits. Sets the UCLK divider.

[000] = UCLK/2.

[001] = UCLK/4.

[010] = UCLK/8.

[011] = UCLK/16.

[100] = UCLK/32.

[101] = UCLK/64.

[110] = UCLK/128.

[111] = UCLK/256.

POINV

Set to 1 by the user to invert all PWM outputs.

Cleared by the user to use PWM outputs as normal.

HOFF

High side off.

Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low.

Cleared by the user to use the PWM outputs as normal.

LCOMP

Load compare registers.

Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of

the PWM timer from 0x00 to 0x01.

Cleared by the user to use the values previously stored in the internal compare registers.

DIR

Direction control.

Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low.

Cleared by the user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low.

HMODE

Enables H-bridge mode.1

Set to 1 by the user to enable H-bridge mode.

Cleared by the user to operate the PWMs in standard mode.

PWMEN

Set to 1 by the user to enable all PWM outputs.

Cleared by the user to disable all PWM outputs.

1 In H-bridge mode, HMODE = 1. See Table 86 to determine the PWM outputs.

Rev. E

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