ADuC7023BCBZ62I-R7 datasheet(88/96 Pages) AD

88 / 96 page

ADuC7023

Data Sheet

| Page 88 of 96

HARDWARE DESIGN CONSIDERATIONS

POWER SUPPLIES

The ADuC7023 operational power supply voltage range is 2.7 V

to 3.6 V. Separate analog and digital power supply pins (AVDD

and IOVDD, respectively) allow AVDD to be kept relatively free of

noisy digital signals often present on the system IOVDD line. In

this mode, the part can also operate with split supplies, that is, it

can use different voltage levels for each supply. For example, the

system can be designed to operate with an IOVDD voltage level

of 3.3 V while the AVDD level can be at 3 V, or vice versa. A

typical split supply configuration is shown in Figure 46.

ADuC7023

IOVDD

AVDD

GNDREF

AGND

IOGND

0.1µF

10µF

DIGITAL SUPPLY

ANALOG SUPPLY

Figure 46. External Dual Supply Connections

As an alternative to providing two separate power supplies, the

user can reduce noise on AVDD by placing a small series resistor

and/or ferrite bead between AVDD and IOVDD, and then decoupling

AVDD separately to ground. An example of this configuration is

shown in Figure 47. With this configuration, other analog circuitry

(such as op amps, voltage reference, and others) can be powered

from the AVDD supply line as well.

ADuC7023

IOVDD

AVDD

GNDREF

AGND

REFGND

IOGND

0.1µF

1.6V

10µF

0.1µF

DIGITAL SUPPLY

BEAD

10µF

Figure 47. External Single Supply Connections

In both Figure 46 and Figure 47, a large value (10 µF) reservoir

capacitor sits on IOVDD, and a separate 10 µF capacitor sits on

AVDD. In addition, local small-value (0.1 µF) capacitors are located

at each AVDD and IOVDD pin of the chip. As per standard design

practice, include all of these capacitors and ensure the smaller

capacitors are close to each AVDD pin with trace lengths as

short as possible. Connect the ground terminal of each of

these capacitors directly to the underlying ground plane.

Finally, the analog and digital ground pins on the ADuC7023

must be referenced to the same system ground reference point

at all times.

IOVDD Supply Sensitivity

The IOVDD supply is sensitive to high frequency noise because it

is the supply source for the internal oscillator and PLL circuits.

When the internal PLL loses lock, the clock source is removed

by a gating circuit from the CPU, and the ARM7TDMI core

stops executing code until the PLL regains lock. This feature is

to ensure that no flash interface timings or ARM7TDMI

timings are violated.

Typically, frequency noise greater than 50 kHz and 50 mV p-p

on top of the supply causes the core to stop working.

If decoupling values recommended in the Power Supplies section

do not sufficiently dampen all noise soures below 50 mV on IOVDD,

a filter such as the one shown in Figure 48 is recommended.

ADuC7023

IOVDD

IOGND

0.1µF

10µF

1µH

DIGITAL

SUPPLY

Figure 48. Recommended IOVDD Supply Filter

Linear Voltage Regulator

Each ADuC7023 requires a single 3.3 V supply, but the core

logic requires a 2.6 V supply. An on-chip linear regulator generates

the 2.6 V from IOVDD for the core logic. The LVDD pin is the 2.6 V

supply for the core logic. An external compensation capacitor of

0.47 µF must be connected between LVDD and DGND (as close

as possible to these pins) to act as a tank of charge, as shown in

Figure 49.

ADuC7023

LVDD

DGND

0.47µF

Figure 49. Voltage Regulator Connections

The LVDD pin should not be used for any other chip. It is also

recommended to use excellent power supply decoupling on

IOVDD to help improve line regulation performance of the

on-chip voltage regulator.

Rev. E

ADuC7023BCBZ62I-R7 датащи(PDF) 88 Page - Analog Devices

ADuC7023BCBZ62I-R7 датащи(HTML) 88 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

датащи скачать

ссылки URL