PIC18F23K22-ESLASHML datasheet(181/496 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 181

PIC18(L)F2X/4XK22

14.2

Compare Mode

The Compare mode function described in this section

is identical for all CCP and ECCP modules available on

this device family.

Compare mode makes use of the 16-bit TimerX

resources, Timer1, Timer3 and Timer5. The 16-bit

value of the CCPRxH:CCPRxL register pair is

constantly compared against the 16-bit value of the

TMRxH:TMRxL register pair. When a match occurs,

one of the following events can occur:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register. At

the same time, the interrupt flag CCPxIF bit is set.

All Compare modes can generate an interrupt.

Figure 14-2 shows a simplified diagram of the

Compare operation.

FIGURE 14-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

14.2.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

Some CCPx outputs are multiplexed on a couple of

pins.

Table 14-2

shows

the

CCP

output

Multiplexing. Selection of the output pin is determined

by the CCPxMX bits in Configuration register 3H

(CONFIG3H). Refer to Register 24-4 for more details.

14.2.2

TimerX MODE RESOURCE

In Compare mode, 16-bit TimerX resource must be

running in either Timer mode or Synchronized Counter

mode. The compare operation may not work in

Asynchronous Counter mode.

See Section 12.0 “Timer1/3/5 Module with Gate

Control” for more information on configuring the 16-bit

TimerX resources.

14.2.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPx module does not

assert control of the CCPx pin (see the CCPxCON

CCPRxH CCPRxL

TMRxH

TMRxL

Comparator

Output

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIR1/2/4)

Match

TRIS

CCPxM<3:0>

Mode Select

Output Enable

Special Event Trigger function on

• ECCP1, ECCP2, ECCP3, CCP4 and CCP5 will:

- Reset TimerX – TMRxH:TMRxL = 0x0000

- TimerX Interrupt Flag, (TMRxIF) is not set

Additional Function on

• CCP5 will

Set ADCON0<1>, GO/DONE bit to start an ADC

Conversion if ADCON<0>, ADON = 1.

CCPx

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

Note:

Clocking TimerX from the system clock

(FOSC) should not be used in Compare

mode. In order for Compare mode to

recognize the trigger event on the CCPx

pin, TImerX must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

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