PIC18F23K22-ESLASHML datasheet(179/496 Pages) MICROCHIP

179 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 179

PIC18(L)F2X/4XK22

14.1.4

CCP PRESCALER

There are four prescaler settings specified by the

CCPxM<3:0> bits of the CCPxCON register. Whenever

the CCP module is turned off, or the CCP module is not

in Capture mode, the prescaler counter is cleared. Any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another does

not clear the prescaler and may generate a false

interrupt. To avoid this unexpected operation, turn the

module off by clearing the CCPxCON register before

changing the prescaler. Example 14-1 demonstrates

the code to perform this function.

EXAMPLE 14-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

14.1.5

CAPTURE DURING SLEEP

Capture mode requires a 16-bit TimerX module for use

as a time base. There are four options for driving the

16-bit TimerX module in Capture mode. It can be driven

by the system clock (FOSC), the instruction clock (FOSC/

4), or by the external clock sources, the Secondary

Oscillator (SOSC), or the TxCKI clock input. When the

16-bit TimerX resource is clocked by FOSC or FOSC/4,

TimerX will not increment during Sleep. When the

device wakes from Sleep, TimerX will continue from its

previous state. Capture mode will operate during Sleep

when the 16-bit TimerX resource is clocked by one of

the external clock sources (SOSC or the TxCKI pin).

#define NEW_CAPT_PS 0x06

//Capture

// Prescale 4th

...

// rising edge

CCPxCON = 0;

// Turn the CCP

// Module Off

CCPxCON = NEW_CAPT_PS;

// Turn CCP module

// on with new

// prescale value

TABLE 14-3:

REGISTERS ASSOCIATED WITH CAPTURE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

CCP1CON

P1M<1:0>

DC1B<1:0>

CCP1M<3:0>

201

CCP2CON

P2M<1:0>

DC2B<1:0>

CCP2M<3:0>

201

CCP3CON

P3M<1:0>

DC3B<1:0>

CCP3M<3:0>

201

CCP4CON

—

DC4B<1:0>

CCP4M<3:0>

201

CCP5CON

—

DC5B<1:0>

CCP5M<3:0>

201

CCPR1H

Capture/Compare/PWM Register 1 High Byte (MSB)

—

CCPR1L

Capture/Compare/PWM Register 1 Low Byte (LSB)

—

CCPR2H

Capture/Compare/PWM Register 2 High Byte (MSB)

—

CCPR2L

Capture/Compare/PWM Register 2 Low Byte (LSB)

—

CCPR3H

Capture/Compare/PWM Register 3 High Byte (MSB)

—

CCPR3L

Capture/Compare/PWM Register 3 Low Byte (LSB)

—

CCPR4H

Capture/Compare/PWM Register 4 High Byte (MSB)

—

CCPR4L

Capture/Compare/PWM Register 4 Low Byte (LSB)

—

CCPR5H

Capture/Compare/PWM Register 5 High Byte (MSB)

—

CCPR5L

Capture/Compare/PWM Register 5 Low Byte (LSB)

—

CCPTMRS0

C3TSEL<1:0>

—

C2TSEL<1:0>

—

C1TSEL<1:0>

204

CCPTMRS1

—

C5TSEL<1:0>

C4TSEL<1:0>

204

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

115

IPR1

—

ADIP

RC1IP

TX1IP

SSP1IP

CCP1IP

TMR2IP

TMR1IP

127

IPR2

OSCFIP

C1IP

C2IP

EEIP

BCL1IP

HLVDIP

TMR3IP

CCP2IP

128

IPR4

—

—CCP5IP

CCP4IP

CCP3IP

130

PIE1

—

ADIE

RC1IE

TX1IE

SSP1IE

CCP1IE

TMR2IE

TMR1IE

123

Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.

Note

These registers/bits are available on PIC18(L)F4XK22 devices.

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