LPC2917SLASH01 datasheet(12/86 Pages) NXP

12 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

12 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

• Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA

advanced peripheral bus) for connection to on-chip peripherals clustered in

subsystems.

• One ARM Peripheral Bus for event router and system control.

The LPC2917/2919/01 conﬁgures the ARM968E-S processor in little-endian byte order.

All peripherals run at their own clock frequency to optimize the total system power

consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer

one transaction deep. This implies that when the ARM968E-S issues a buffered write

action to a register located on the APB side of the bridge, it continues even though the

actual write may not yet have taken place. Completion of a second write to the same

subsystem will not be executed until the ﬁrst write is ﬁnished.

6.2 ARM968E-S processor

The ARM968E-S is a general purpose 32-bit RISC processor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers (CISC). This simplicity results in a high instruction throughput

and impressive real-time interrupt response from a small and cost-effective controller

core.

Amongst the most compelling features of the ARM968E-S are:

• Separate directly connected instruction and data Tightly Coupled Memory (TCM)

interfaces

• Write buffers for the AHB and TCM buses

• Enhanced 16

× 32 multiplier capable of single-cycle MAC operations and 16-bit ﬁxed-

point DSP instructions to accelerate signal-processing algorithms and applications.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. The ARM968E-S is based on the ARMv5TE ﬁve-stage pipeline

architecture. Typically, in a three-stage pipeline architecture, while one instruction is being

executed its successor is being decoded and a third instruction is being fetched from

memory. In the ﬁve-stage pipeline additional stages are added for memory access and

write-back cycles.

The ARM968E-S processor also employs a unique architectural strategy known as

THUMB, which makes it ideally suited to high-volume applications with memory

restrictions or to applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the

ARM968E-S processor has two instruction sets:

• Standard 32-bit ARMv5TE set

• 16-bit THUMB set

The THUMB set's 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM's performance advantage over a

traditional 16-bit controller using 16-bit registers. This is possible because THUMB code

operates on the same 32-bit register set as ARM code.

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