LPC2917SLASH01 datasheet(61/86 Pages) NXP

61 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

61 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

[1]

All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb =85 °Conwafer

level. Cased products are tested at Tamb =25 °C (ﬁnal testing). Both pre-testing and ﬁnal testing use correlated test conditions to cover

the speciﬁed temperature and power-supply voltage range.

[2]

Leakage current is exponential to temperature; worst-case value is at 85

°C Tvj. All clocks off. Analog modules and FLASH powered

down.

[3]

Not 5 V-tolerant when pull-up is on.

[4]

For I/O Port 0, the maximum input voltage is deﬁned by VI(ADC).

[5]

For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input

capacitance to ADC.

[6]

Cxtal is crystal load capacitance and Cext are the two external load capacitors.

Vhys

hysteresis voltage

0.4

ILIH

HIGH-level input leakage

current

µA

ILIL

LOW-level input leakage

current

µA

II(pd)

pull-down input current

all port pins, VI = 3.3 V;

VI = 5.5 V; see Figure 23

100

µA

II(pu)

pull-up input current

all port pins, RST,

TRST, TDI, JTAGSEL,

TMS: VI =0V; VI > 3.6 V

is not allowed; see

Figure 24

−25

−50

−115

µA

input capacitance

[5] -3

Output pins and I/O pins conﬁgured as output

output voltage

VDD(IO)

VOH

HIGH-level output voltage IOH = −4mA

VDD(IO) – 0.4

VOL

LOW-level output voltage

IOL = 4 mA

0.4

load capacitance

Oscillator

VXIN_OSC

voltage on pin XIN_OSC

1.8

Rs(xtal)

crystal series resistance

fosc = 10 MHz to 15 MHz

[6]

Cxtal =10pF;

Cext =18pF

160

Ω

Cxtal =20pF;

Cext =39pF

Ω

fosc = 15 MHz to 20 MHz

[6]

Cxtal =10pF;

Cext =18pF

Ω

input capacitance

of XIN_OSC

[7] -2

Power-up reset

Vtrip(high)

high trip level voltage

[8] 1.1

1.4

1.6

Vtrip(low)

low trip level voltage

[8] 1.0

1.3

1.5

Vtrip(dif)

difference between high

and low trip level voltage

[8] 50

120

180

Table 33.

Static characteristics …continued

VDD(CORE) =VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; Tvj = -40 °Cto+85 °C; all voltages are

measured with respect to ground; positive currents ﬂow into the IC; unless otherwise speciﬁed.[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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