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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC2917/01 датащи(PDF) 18 Page - NXP Semiconductors |
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LPC2917/01 датащи(HTML) 18 Page - NXP Semiconductors |
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18 / 86 page  LPC2917_19_01_2 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 02 — 17 June 2009 18 of 86 NXP Semiconductors LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN 6.7.2 Base clock and branch clock relationship Table 7 and Table 8 contain an overview of all the base blocks in the LPC2917/2919/01 and their derived branch clocks. In relevant cases more detailed information can be found in the specific subsystem description. Some branch clocks have special protection since they clock vital system parts of the device and should (for example) not be switched off. See Section 6.15.5 for more details of how to control the individual branch clocks. Table 7. CGU0 generated base clock and branch clock overview Base clock Branch clock name Parts of the device clocked by this branch clock Remark BASE_SAFE_CLK CLK_SAFE watchdog timer [1] BASE_SYS_CLK CLK_SYS_CPU ARM968E-S and TCMs CLK_SYS_SYS AHB bus infrastructure CLK_SYS_PCRSS AHB side of bridge in PCRSS CLK_SYS_FMC Flash-Memory Controller CLK_SYS_RAM0 Embedded SRAM Controller 0 (32 kB) CLK_SYS_RAM1 Embedded SRAM Controller 1 (16 kB) CLK_SYS_SMC External Static-Memory Controller CLK_SYS_GESS General Subsystem CLK_SYS_VIC Vectored Interrupt Controller CLK_SYS_PESS Peripheral Subsystem [2] [4] CLK_SYS_GPIO0 GPIO bank 0 CLK_SYS_GPIO1 GPIO bank 1 CLK_SYS_GPIO2 GPIO bank 2 CLK_SYS_GPIO3 GPIO bank 3 CLK_SYS_IVNSS_A AHB side of bridge of IVNSS CLK_SYS_MSCSS_A AHB side of bridge of MSCSS CLK_SYS_DMA GPDMA BASE_PCR_CLK CLK_PCR_SLOW PCRSS, CGU, RGU and PMU logic clock [1], [3] BASE_IVNSS_CLK CLK_IVNSS_APB APB side of the IVNSS CLK_IVNSS_CANCA CAN controller Acceptance Filter CLK_IVNSS_CANC0 CAN channel 0 CLK_IVNSS_CANC1 CAN channel 1 CLK_IVNSS_I2C0 I2C0 CLK_IVNSS_I2C1 I2C1 CLK_IVNSS_LIN0 LIN channel 0 CLK_IVNSS_LIN1 LIN channel 1 |
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