LPC2917SLASH01 datasheet(62/86 Pages) NXP

62 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

62 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

[7]

This parameter is not part of production testing or ﬁnal testing, hence only a typical value is stated. Maximum and minimum values are

based on simulation results.

[8]

The power-up reset has a time ﬁlter: VDD(CORE) must be above Vtrip(high) for 2 µs before reset is de-asserted; VDD(CORE) must be below

Vtrip(low) for 11 µs before internal reset is asserted.

[1]

Conditions: VSS(IO) =0V, VDDA(ADC3V3) = 3.3 V.

[2]

The ADC is monotonic, there are no missing codes.

[3]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 17.

[4]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 17.

[5]

The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 17.

[6]

The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 17.

[7]

The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC

and the ideal transfer curve. See Figure 17.

[8]

See Figure 16.

Table 34.

ADC static characteristics

VDDA(ADC3V3) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise speciﬁed; ADC frequency 4.5 MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VVREFN

voltage on pin VREFN

VVREFP − 2V

VVREFP

voltage on pin VREFP

VVREFN +2 -

VDDA(ADC3V3)

input impedance

between VVREFN and

VVREFP

4.4

Ω

VIA

analog input voltage

VVREFN

-VVREFP

Cia

analog input capacitance

differential linearity error

[1][2][3]

±1

LSB

EL(adj)

integral non-linearity

[1][4] --

±2

LSB

offset error

[1][5] --

±3

LSB

gain error

[1][6] --

±0.5

absolute error

[1][7] --

±4

LSB

Rvsi

voltage source interface

resistance

[8] -

Ω

Fig 16. Suggested ADC interface - LPC2917/2919/01 ADC1/2 IN[y] pin

LPC2XXX

ADC IN[y]SAMPLE

ADC IN[y]

20 k

Ω

3 pF

5 pF

Rvsi

VSS(IO), VSS(CORE)

VEXT

002aae280

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