LPC2917SLASH01 datasheet(32/86 Pages) NXP

32 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

32 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

• Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts

• Serial clock-rate master mode: fserial_clk

≤ f

clk(SPI)/2

• Serial clock-rate slave mode: fserial_clk = fclk(SPI)/4

• Internal loopback test mode

The SPI module can operate in:

• Master mode:

– Normal transmission mode

– Sequential slave mode

• Slave mode

6.12.5.1

Functional description

The SPI module is a master or slave interface for synchronous serial communication with

peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial

Interfaces.

The SPI module performs serial-to-parallel conversion on data received from a peripheral

device. The transmit and receive paths are buffered with FIFO memories (16 bits wide

32 words deep). Serial data is transmitted on pins SDOx and received on pins SDIx.

The SPI module includes a programmable bit-rate clock divider and prescaler to generate

the SPI serial clock from the input clock CLK_SPIx.

The SPI module’s operating mode, frame format, and word size are programmed through

the SLVn_SETTINGS registers.

A single combined interrupt request SPI_INTREQ output is asserted if any of the

interrupts are asserted and unmasked.

Depending on the operating mode selected, the SPI SCS outputs operate as an

active-HIGH frame synchronization output for Texas Instruments synchronous serial

frame format or an active LOW chip select for SPI.

Each data frame is between four and 16 bits long, depending on the size of words

programmed, and is transmitted starting with the MSB.

6.12.5.2

Pin description

The SPI pins are combined with other functions on the port pins of the LPC2917/2919/01,

see Section 6.11.3. Table 17 shows the SPI pins (x runs from 0 to 2; y runs from 0 to 3).

[1]

Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in

master mode, input in slave mode.

[2]

In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in

slave mode.

Table 17.

SPI pins

Symbol

Pin name

Direction

Description

SPIx SCSy

SCSx[y]

IN/OUT

SPIx chip select[1][2]

SPIx SCK

SCKx

IN/OUT

SPIx clock[1]

SPIx SDI

SDIx

SPIx data input

SPIx SDO

SDOx

OUT

SPIx data output

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