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LPC2917/01 датащи(PDF) 28 Page - NXP Semiconductors

номер детали LPC2917/01
подробное описание детали  ARM9 microcontroller with CAN and LIN
PDF  86 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC2917/01 датащи(HTML) 28 Page - NXP Semiconductors

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LPC2917_19_01_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 June 2009
28 of 86
NXP Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
The vectored interrupt-controller inputs are active HIGH.
6.11.4.1
Pin description
The event router module in the LPC2917/2919/01 is connected to the pins listed below.
The pins are combined with other functions on the port pins of the LPC2917/2919/01.
Table 14 shows the pins connected to the event router, and also the corresponding bit
position in the event-router registers and the default polarity.
6.12 Peripheral subsystem
6.12.1 Peripheral subsystem clock description
The peripheral subsystem is clocked by a number of different clocks:
• CLK_SYS_PESS
• CLK_UART0/1
• CLK_SPI0/1/2
• CLK_TMR0/1/2/3
• CLK_SAFE see Section 6.7.2
6.12.2 Watchdog timer
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
• Internal chip reset if not periodically triggered
• Timer counter register runs on always-on safe clock
Table 14.
Event-router pin connections
Symbol
Direction
Description
Default polarity
EXTINT 7 - 0
IN
external interrupt input 7 - 0
1
CAN0 RXD
IN
CAN0 receive data input wake-up
0
CAN1 RXD
IN
CAN1 receive data input wake-up
0
I2C0_SCL
IN
I2C0 SCL clock input
0
I2C1_SCL
IN
I2C1 SCL clock input
0
LIN0 RXD
IN
LIN0 receive data input wake-up
0
LIN1 RXD
IN
LIN1 receive data input wake-up
0
SPI0 SDI
IN
SPI0 receive data input
0
SPI1 SDI
IN
SPI1 receive data input
0
SPI2 SDI
IN
SPI2 receive data input
0
UART0 RXD
IN
UART0 receive data input
0
UART1 RXD
IN
UART1 receive data input
0
-
na
CAN interrupt (internal)
1
-
na
VIC FIQ (internal)
1
-
na
VIC IRQ (internal)
1



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