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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC2917/01 датащи(PDF) 72 Page - NXP Semiconductors |
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LPC2917/01 датащи(HTML) 72 Page - NXP Semiconductors |
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72 / 86 page  LPC2917_19_01_2 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 02 — 17 June 2009 72 of 86 NXP Semiconductors LPC2917/01; LPC2919/01 ARM9 microcontroller with CAN and LIN 9.5 Dynamic characteristics: external static memory [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb =85 °C ambient temperature on wafer level. Cased products are tested at Tamb =25 °C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. [2] When the byte lane select signals are used to connect the write enable input (8 bit devices), tCSHBLSH = −0.5 × TCLCL. [3] When the byte lane select signals are used to connect the write enable input (8 bit devices), tCSLBLSL = tCSLWEL. [4] For 16 and 32 bit devices. Table 40. External static memory interface dynamic characteristics VDD(CORE) =VDD(OSC_PLL); VDD(IO) = 2.7 V to 3.6 V; VDDA(ADC3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.[1] Symbol Parameter Conditions Min Typ Max Unit TCLCL clock cycle time 8 - 100 ns ta(R)int internal read access time - - 20.5 ns ta(W)int internal write access time - - 24.9 ns Read cycle parameters tCSLAV CS LOW to address valid time −5 −2.5 - ns tOELAV OE LOW to address valid time −5 − WSTOEN × T CLCL −2.5 − WSTOEN × T CLCL -ns tCSLOEL CS LOW to OE LOW time - 0 + WSTOEN × T CLCL -ns tsu(DQ) data input /output set-up time 11 16 22 ns th(D) data input hold time 0 2.5 5 ns tCSHOEH CS HIGH to OE HIGH time - 0 - ns tBLSLBLSH BLS LOW to BLS HIGH time - (WST1 − WSTOEN +1) × TCLCL -ns tOELOEH OE LOW to OE HIGH time - (WST1 − WSTOEN +1) × TCLCL -ns tBLSLAV BLS LOW to address valid time - 0 + WSTOEN × TCLCL -ns Write cycle parameters tCSHBLSH CS HIGH to BLS HIGH time [2] -0 - ns tCSLWEL CS LOW to WE LOW time - (WSTWEN + 0.5) × TCLCL -ns tCSLBLSL CS LOW to BLS LOW time [3] - WSTWEN × TCLCL -ns tWELDV WE LOW to data valid time - (WSTWEN + 0.5) × TCLCL -ns tCSLDV CS LOW to data valid time −0.5 −0.1 0.3 ns tWELWEH WE LOW to WE HIGH time - (WST2 − WSTWEN +1) × TCLCL -ns tBLSLBLSH BLS LOW to BLS HIGH time [4] - (WST2 - WSTWEN +2) × TCLCL -ns |
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