LPC2917SLASH01 datasheet(39/86 Pages) NXP

39 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

39 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

6.14.2 Pin description

The pins of the LPC2917/2919/01 MSCSS associated with the two ADC modules are

described in Section 6.14.4.2. Pins connected to the four PWM modules are described in

Section 6.14.5.4, pins directly connected to the MSCSS timer 1 module are described in

Section 6.14.6.1, and pins connected to the quadrature encoder interface are described in

Section 6.14.7.1.

6.14.3 Clock description

The MSCSS is clocked from a number of different sources:

• CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge

• CLK_MSCSS_APB clocks the subsystem APB bus

• CLK_MSCSS_MTMR0/1 clocks the timers

• CLK_MSCSS_PWM0..3 clocks the PWMs.

Each ADC has two clock areas; a APB part clocked by CLK_MSCSS_ADCx_APB (x = 1

or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see

Section 6.7.2.

All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A

which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived

from BASE_CLK_ADC. If speciﬁc PWM or ADC modules are not used their corresponding

clocks can be switched off.

6.14.4 Analog-to-digital converter

The MSCSS in the LPC2917/2919/01 includes two 10-bit successive-approximation

analog-to-digital converters.

The key features of the ADC interface module are:

• ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to

3.3 V

• External reference-level inputs

• 400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at

2-bit resolution

• Programmable resolution from 2-bit to 10-bit

• Single analog-to-digital conversion scan mode and continuous analog-to-digital

conversion scan mode

• Optional conversion on transition on external start input, timer capture/match signal,

PWM_sync or ‘previous’ ADC

• Converted digital values are stored in a register for each channel

• Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’

compare-value indication for each channel

• Power-down mode

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