LPC2917SLASH01 datasheet(24/86 Pages) NXP

24 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

24 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

6.9.2 Pin description

The external static-memory controller module in the LPC2917/2919/01 has the following

pins, which are combined with other functions on the port pins of the LPC2917/2919/01.

Table 13 shows the external memory controller pins.

6.9.3 Clock description

The External Static-Memory Controller is clocked by CLK_SYS_SMC, see Section 6.7.2.

6.9.4 External memory timing diagrams

A timing diagram for reading from external memory is shown in Figure 5. The relationship

between the wait-state settings is indicated with arrows.

Table 11.

External memory-bank address bit description

32-bit

system

address bit

ﬁeld

Symbol

Description

31 to 29

BA[2:0]

external static-memory base address (three most signiﬁcant bits);

the base address can be found in the memory map; see Ref. 1. This

ﬁeld contains ‘010’ when addressing an external memory bank.

28 to 26

CS[2:0]

chip select address space for eight memory banks; see Ref. 1.

25 and 24

always ‘00’; other values are ‘mirrors’ of the 16 MB bank address.

23 to 0

A[23:0]

16 MB memory banks address space

Table 12.

External static-memory controller banks

CS[2:0]

Bank

000

bank 0

001

bank 1

010

bank 2

011

bank 3

100

bank 4

101

bank 5

110

bank 6

111

bank 7

Table 13.

External memory controller pins

Symbol

Direction

Description

EXTBUS CSx

OUT

memory-bank x select, x runs from 0 to 7

EXTBUS BLSy

OUT

byte-lane select input y, y runs from 0 to 3

EXTBUS WE

OUT

write enable (active LOW)

EXTBUS OE

OUT

output enable (active LOW)

EXTBUS A[23:0] OUT

address bus

EXTBUS D[31:0] IN/OUT

data bus

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