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TMS320VC549 датащи(PDF) 100 Page - Texas Instruments |
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TMS320VC549 датащи(HTML) 100 Page - Texas Instruments |
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100 / 111 page ![]() TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 serial-port transmit timing in TDM mode (continued) timing requirements for serial-port transmit in TDM mode [H = 0.5tc(CO)] (see Figure 39) ’C54x-40 ’LC54x-40 ’LC54x-50 ’54X–66 UNIT MIN MAX MIN MAX tc(SCK) Cycle time, serial-port clock 8H† ‡ 16H† ‡ ns tf(SCK) Fall time, serial-port clock 6 6 ns tr(SCK) Rise time, serial-port clock 6 6 ns tw(SCK) Pulse duration, serial-port clock low/high 4H† 8H† ns † When SCK is generated internally, this value is typical. ‡ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching 1. It is characterized approaching an input frequency of 0 Hz but tested as a much higher frequency to minimize test time. A7 B2 B8 B7 A3 B12 A2 A0 A1 B0 B1 B13 B14 B0 tw(SCK) tw(SCK) th(TCH-TDV) td(TCH-TFV) TFRM TADD TDAT TCLK B15 tc(SCK) td(TC-TDV) th(TCH-TDV) td(TCH-TFV) td(TC-TDV) tr(SCK) tf(SCK) Figure 39. Serial-Port Transmit Timing in TDM Mode |
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