TMS320VC549 datasheet(28/111 Pages) TI

28 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

bootloader (continued)

The bootloader provided in the on-chip ROM of the ’548 and ’549 devices implements several enhanced

features. These include the addition of BSP and TDM boot modes. To accommodate these new boot modes,

the encoding of the boot-mode selection word has been modified.

For a detailed description of bootloader functionality, refer to the

TMS320C54x DSP Reference Set, Volume 4:

Applications Guide (literature number SPRU173). For a detailed description of the enhanced bootloader

functionality, refer to the

TMS320x548/’549 Bootloader Technical Reference.

on-chip peripherals

All the ’54x devices have the same CPU structure; however, they have different on-chip peripherals connected

to their CPUs. The on-chip peripheral options provided are:

D Software-programmable wait-state generator

D Programmable bank switching

D Parallel I/O ports

D Serial ports (standard, TDM, and BSP)

D A hardware timer

D A clock generator [with a multiple phase-locked loop (PLL) on ’549 devices]

software-programmable wait-state generators

Software-programmable wait-state generators can be used to extend external bus cycles up to seven machine

cycles to interface with slower off-chip memory and I / O devices. The software wait-state generators are

incorporated without any external hardware. For off-chip memory access, a number of wait states can be

specified for every 32K-word block of program and data memory space, and for one 64K-word block of I / O

space within the software wait-state (SWWSR) register.

programmable bank-switching

Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank

boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from

program-memory space to data-memory space (’54x) or one program memory page to another program

memory page (’548 and ’549 only). This extra cycle allows memory devices to release the bus before other

devices start driving the bus; thereby avoiding bus contention. The size of memory bank for the bank-switching

is defined by the bank-switching control register (BSCR).

parallel I / O ports

Each ’54x device has a total of 64K I / O ports. These ports can be addressed by the PORTR instruction or the

PORTW instruction. The IS signal indicates a read / write operation through an I / O port. The devices can

interface easily with external devices through the I / O ports while requiring minimal off-chip address-decoding

circuits.

host-port interface (’542, ’545, ’548, and ’549 only)

The host-port interface (HPI) is an 8-bit parallel port used to interface a host processor to the DSP device.

Information is exchanged between the DSP device and the host processor through on-chip memory that is

accessible by both the host and the DSP device. The DSP devices have access to the HPI control (HPIC)

2K-word DARAM block that resides at 1000h to 17FFh in data memory and can also be used as

general-purpose on-chip data or program DARAM.

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