TMS320VC549 datasheet(18/111 Pages) TI

18 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

central processing unit (CPU)

The CPU of the ’54x devices contains:

D A 40-bit arithmetic logic unit (ALU)

D Two 40-bit accumulators

D A barrel shifter

D A 17 × 17-bit multiplier/adder

D A compare, select and store unit (CSSU)

arithmetic logic unit (ALU)

The ’54x devices perform 2s-complement arithmetic using: a 40-bit arithmetic logic unit (ALU) and two 40-bit

accumulators (ACCA and ACCB). The ALU also can perform Boolean operations.

The ALU can function as two 16-bit ALUs and perform two 16-bit operations simultaneously when the C16 bit

in status register 1 (ST1) is set.

accumulators

The accumulators, ACCA and ACCB, store the output from the ALU or the multiplier / adder block; the

accumulators can also provide a second input to the ALU or the multiplier / adder. The accumulators are divided

into three parts:

D Guard bits (bits 32–39)

D A high-order word (bits 16–31)

D A low-order word (bits 0–15)

Instructions are provided for storing the guard bits, the high- and the low-order accumulator words in data

memory, and for manipulating 32-bit accumulator words in or out of data memory. Also, any of the accumulators

can be used as temporary storage for the other.

barrel shifter

The ’54x ’s barrel shifter has a 40-bit input connected to the accumulator, or data memory

(CB, DB) and a 40-bit output connected to the ALU, or data memory (EB). The barrel shifter produces a left shift

of 0 to 31 bits and a right shift of 0 to 16 bits on the input data. The shift requirements are defined in the shift-count

field (ASM) of ST1 or defined in the temporary register (TREG), which is designated as a shift-count register.

This shifter and the exponent detector normalize the values in an accumulator in a single cycle. The least

significant bits (LSBs) of the output are filled with 0s and the most significant bits (MSBs) can be either zero-filled

or sign-extended, depending on the state of the sign-extended mode bit (SXM) of ST1. Additional shift

capabilities enable the processor to perform numerical scaling, bit extraction, extended arithmetic, and overflow

prevention operations.

multiplier / adder

The multiplier / adder performs 17

× 17-bit 2s-complement multiplication with a 40-bit accumulation in a single

instruction cycle. The multiplier / adder block consists of several elements: a multiplier, adder, signed / unsigned

input control, fractional control, a zero detector, a rounder (2s-complement), overflow / saturation logic, and

TREG. The multiplier has two inputs: one input is selected from the TREG, a data-memory operand, or an

accumulator; the other is selected from the program memory, the data memory, an accumulator, or an

immediate value. The fast on-chip multiplier allows the ’54x to perform operations such as convolution,

correlation, and filtering efficiently.

In addition, the multiplier and ALU together execute multiply / accumulate (MAC) computations and ALU

operations in parallel in a single instruction cycle. This function is used in determining the Euclid distance, and

in implementing symmetrical and least mean square (LMS) filters, which are required for complex DSP

algorithms.

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