TMS320VC549 datasheet(35/111 Pages) TI

35 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

use of the PLLCOUNT programmable lock timer (continued)

100

2.5

’549 Only

CLKOUT Frequency (MHz)

Figure 8. PLL Lockup Time Versus CLKOUT Frequency

switching from DIV mode to PLL mode

Several circumstances may require switching from DIV mode to PLL mode; however, note that if the PLL is not

locked when switching from DIV mode to PLL mode, the PLL lockup time delay must be observed before the

mode switch occurs to ensure that only proper clock signals are sent to the device. It is, therefore, important

to know whether or not the PLL is locked when switching operating modes.

The PLL is unlocked on power-up, after changing the PLLMUL or PLLDIV values, after turning off the PLL

(PLLON/OFF = 0), or after loss of input reference clock. Once locked, the PLL remains locked even in DIV mode

as long as the PLL had been previously locked and has not been turned off (PLLON/OFF stays 1), and the

PLLMUL and PLLDIV values have not been changed since the PLL was locked.

Switching from DIV mode to PLL mode (setting PLLNDIV to 1) activates the PLLCOUNT programmable lock

timer (when PLLCOUNT is preloaded with a non-zero value), and this can be used to provide a convenient

method for implementing the lockup time delay. The PLLCOUNT lock timer feature should be used in the

situations described above, where the PLL is unlocked unless a reset delay is used to implement the lockup

delay, or the PLL is not used.

Switching from DIV mode to PLL mode is accomplished by loading the CLKMD register. The following procedure

describes switching from DIV mode to PLL mode when the PLL is not locked. When performing this mode switch

with the PLL already locked, the effect is the same as when switching from PLL to DIV mode, but in the reverse

order. In this case, the delays of when the new clock mode takes effect are the same.

When switching from DIV to PLL mode with the PLL unlocked, or when the mode change will result in unlocked

operation, the PLLMUL[3–0], PLLDIV, and PLLNDIV bits are set to select the desired frequency multiplier as

described in Table 5, and the PLLCOUNT[7–0] bits are set to select the required lockup time delay. Note that

PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF can only be modified when in DIV mode.

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