TMS320VC549 datasheet(71/111 Pages) TI

71 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a memory write

(MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 17)

PARAMETER

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN

MAX

MIN

MAX

td(CLKH-A)

Delay time, address valid from CLKOUT high§

– 2

td(CLKL-A)

Delay time, address valid from CLKOUT low¶

td(CLKL-MSL)

Delay time, MSTRB low from CLKOUT low

td(CLKL-D)W

Delay time, data valid from CLKOUT low

td(CLKL-MSH)

Delay time, MSTRB high from CLKOUT low

– 2

td(CLKH-RWL)

Delay time, R/W low from CLKOUT high

– 2

td(CLKH-RWH)

Delay time, R/W high from CLKOUT high

– 2

td(RWL-MSTRBL)

Delay time, MSTRB low after R/W low

H – 2

H + 3

H – 2

H + 3

th(A)W

Hold time, address valid after CLKOUT high§

th(D)MSH

Hold time, write data valid after MSTRB high

H–5

H+5¶

H–5

H+5¶

tw(SL)MS

Pulse duration, MSTRB low

2H – 5

2H–5

tsu(A)W

Setup time, address valid before MSTRB low

2H – 5

2H–5

tsu(D)MSH

Setup time, write data valid before MSTRB high

2H – 10

2H + 10¶

2H–10

2H+8§

† Address, PS, and DS timings are all included in timings referenced as address.

‡ See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

§ In the case of a memory write preceded by a memory write.

¶ In the case of a memory write preceded by an I/O cycle.

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