TMS320VC549 datasheet(102/111 Pages) TI

102 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

102

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

host-port interface timing (continued)

timing requirements for host-port interface [H = 0.5tc(CO)] (see Note 5 and Figure 40 through

Figure 43)

’C54x-40

’C54x-50

’C54x-66

UNIT

MIN

MAX

tsu(HBV-DSL)

Setup time, HAD / HBIL valid before DS or HAS falling edge

th(DSL-HBV)

Hold time, HAD / HBIL valid after DS or HAS falling edge

tsu(HSL-DSL)

Setup time, HAS low before DS falling edge

tw(DSL)

Pulse duration, DS low

30†

tw(DSH)

Pulse duration, DS high

Cycle time DS rising edge to next DS

Case 1: HOM access timings

(see Access Timing Without HRDY)

tc(DSH-DSH)†

Cycle time, DS rising edge to next DS

rising edge

Case 2a: SAM accesses and HOM active writes

to DSPINT or HINT.

(see Access Timings With HRDY)

10H

tsu(HDV-DSH)

Setup time, HD valid before DS rising edge

td(DSH-HSL)‡

Delay time, DS high to next HAS low

10H

th(DSH – HDV)W

Hold time, HD valid after DS rising edge, write

† A host not using HRDY should meet the 10H requirement all the time unless a software handshake is used to change the access rate according

to the HPI mode.

‡ Must only be met if HAS is going low when not accessing the HPI (as would be the case where multiple devices are being driven by one host).

NOTE 5: SAM = shared-access mode, HOM = host-only mode

HAD stands for HCNTRL0, HCNTRL1, and HR / W.

HDS refers to either HDS1 or HDS2.

DS refers to the logical OR of HCS and HDS.

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