TMS320VC549 datasheet(64/111 Pages) TI

64 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

divide-by-two/divide-by-four clock option – PLL disabled

The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to

generate the internal machine cycle. The selection of the clock mode is described in the clock generator section.

When an external clock source is used, the frequency injected must conform to specifications listed in the timing

requirements table.

switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 13

and Figure 14, and the recommended operating conditions table)

PARAMETER

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

25‡

2tc(CI)

†

20‡

2tc(CI)

†

15‡

2tc(CI)

†

td(CIH-CO)

Delay time, X2/CLKIN high to

CLKOUT high/low

tf(CO)

Fall time, CLKOUT†

tr(CO)

Rise time, CLKOUT†

tw(COL)

Pulse duration, CLKOUT low†

H–4

H–2

H–4

H–2

H–4

H–2

tw(COH)

Pulse duration, CLKOUT high†

H–4

H–2

H–4

H–2

H–4

H–2

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

‡ It is recommended that the PLL clocking option be used for maximum frequency operation.

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