TMS320VC549 datasheet(37/111 Pages) TI

37 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

switching mode from one PLL multiplier to another (continued)

Also, note that a direct switch between divide-by-two mode and divide-by-four mode is not possible. To switch

between these two modes, the clock generator must first be set to PLL mode with an integer-only

(non-fractional) multiplier ratio, and then set back to DIV mode in the desired divider configuration (see previous

sections for details on switching between DIV and PLL modes).

The following software example shows a code sequence that can be used to switch clock mode from PLL

× X

to PLL

× 1.

STM

#0b, CLKMD

;switch to DIV mode

TstStatu:

LDM

CLKMD, A

AND

#01b, A

;poll STATUS bit

TstStatu, ANEQ

STM

#0000001111101111b, CLKMD

;switch to PLL

1 mode

programmable clock generator operation immediately following reset

Immediately following reset, the operating mode of the clock generator is determined only on the basis of the

CLKMD1/2/3 pin state as described in Table 6. All but two of these operating modes are ’divide-by-two with

external source’. Switching from divide-by-two to a PLL mode can easily be accomplished by changing the

CLKMD register contents. Note that if use of the internal oscillator is desired, either the 100 or the 111 state of

the CLKMD1– CLKMD3 pins must be selected at reset (as shown in Table 6) since the internal oscillator cannot

be programmed through software.

The following software example shows an instruction that can be used to switch from divide-by-two mode to

the PLL

3 mode.

STM

#0010000101001111b, CLKMD

considerations when using IDLE1/IDLE2/IDLE3

When using one of the IDLE instructions to reduce power requirements, proper management of the PLL is

important. The clock generator consumes the least power when operating in DIV mode with the PLL disabled.

Therefore, if power dissipation is a significant consideration, it is desirable to switch from PLL to DIV mode, and

disable the PLL, before executing the IDLE1/IDLE2/IDLE3 instructions. This is accomplished as explained

above in the section describing switching clock mode from PLL to DIV. After waking up from

IDLE1/IDLE2/IDLE3, the clock generator can be reprogrammed to PLL mode as explained above in the section

describing switching clock mode from DIV to PLL.

Note that when the PLL is stopped during an IDLE state, and the ’54x device is restarted and the clock generator

is switched back to PLL mode, the PLL lockup delay occurs in the same manner as in a normal device startup.

Therefore, in this case, the lockup delay must also be accounted for, either externally or by using the PLL lockup

counter timer.

The following software example illustrates a code sequence that switches the clock generator from PLL

mode to divide-by-two mode, turns off the PLL, and enters IDLE3. After waking up from IDLE3, the clock

generator is switched back from DIV mode to PLL

3 mode using a single STM instruction, with a PLLCOUNT

of 64 (decimal) used for the lock timer value.

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