TMS320VC549 datasheet(16/111 Pages) TI

16 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

’54x Signal Descriptions (Continued)

TERMINAL

DESCRIPTION

NAME

DESCRIPTION

TYPE†

IEEE1149.1 TEST PINS

TCK

IEEE standard 1149.1 test clock. Pin with internal pullup device. This is normally a free-running clock signal with

a 50% duty cycle. The changes on the test-access port (TAP) of input signals TMS and TDI are clocked into the

TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP

output signal (TDO) occur on the falling edge of TCK.

TDI

IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

TDO

O/Z

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out

of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in

progress. TDO also goes into the high-impedance state when EMU1/OFF is low.

TMS

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into

the TAP controller on the rising edge of TCK.

TRST

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the

operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and

the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

EMU0

I/O/Z

Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF

condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined

as input/output by way of IEEE standard 1149.1 scan system.

EMU1/OFF

I/O/Z

Emulator interrupt 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or

from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When

TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output

drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not

for multiprocessing applications). Therefore, for the OFF condition, the following conditions apply:

TRST = low,

EMU0 = high

EMU1/OFF = low

DEVICE TEST PIN

TEST1

Test1 – Reserved for internal use only (’LC548, ’LC549, and ’VC549 only). This pin must not be connected

(NC).

† I = Input, O = Output, Z = High impedance

architecture

The ’54x DSPs use an advanced, modified Harvard architecture that maximizes processing power by

maintaining three separate bus structures for data memory and one for program memory. Separate program

and data spaces allow simultaneous access to program instructions and data, providing a high degree of

parallelism. For example, two read and one write operations can be performed in a single cycle. Instructions

with parallel store and application-specific instructions fully utilize this architecture. In addition, data can be

transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,

and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’54x include

the control mechanisms to manage interrupts, repeated operations, and function calls.

The functional block diagram includes the principal blocks and bus structure in the ’54x devices.

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