TMS320VC549 datasheet(19/111 Pages) TI

19 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

compare, select and store unit (CSSU)

The compare, select and store unit (CSSU) performs maximum comparisons between the accumulator’s high

and low word, allows the test / control (TC) flag bit of status register 0 (ST0) and the transition (TRN) register

to keep their transition histories, and selects the larger word in the accumulator to be stored in data memory.

The CSSU also accelerates Viterbi-type butterfly computation with optimized on-chip hardware.

program control

Program control is provided by several hardware and software mechanisms:

D The program controller decodes instructions, manages the pipeline, stores the status of operations, and

decodes conditional operations. Some of the hardware elements included in the program controller are the

program counter, the status and control register, the stack, and the address-generation logic.

D Some of the software mechanisms used for program control include branches, calls, conditional

instructions, a repeat instruction, reset, and interrupts.

power-down modes

There are three power-down modes, activated by the IDLE1, IDLE2, and IDLE3 instructions. In these modes,

the ’54x devices enter a dormant state and dissipate considerably less power than in normal operation. The

IDLE1 instruction is used to shut down the CPU. The IDLE2 instruction is used to shut down the CPU and on-chip

peripherals. The IDLE3 instruction is used to shut down the ’54x processor completely. This instruction stops

the PLL circuitry as well as the CPU and peripherals.

bus structure

The ’54x device architecture is built around eight major 16-bit buses:

D One program-read bus (PB), which carries the instruction code and immediate operands from program

memory

D Two data-read buses (CB, DB) and one data-write bus (EB), which interconnect to various elements, such

as the CPU, data-address generation logic, program-address generation logic, on-chip peripherals, and

data memory

–

The CB and DB carry the operands read from data memory.

–

The EB carries the data to be written to memory.

D Four address buses (PAB, CAB, DAB, and EAB), which carry the addresses needed for instruction

execution

The ’54x devices have the capability to generate up to two data-memory addresses per cycle, which are stored

into two auxiliary register arithmetic units (ARAU0 and ARAU1).

The PB can carry data operands stored in program space (for instance, a coefficient table) to the multiplier for

multiply / accumulate operations or to a destination in data space for the data move instruction. This capability

allows implementation of single-cycle three-operand instructions such as FIRS.

The ’54x devices also have an on-chip bidirectional bus for accessing on-chip peripherals; this bus is connected

to DB and EB through the bus exchanger in the CPU interface. Accesses using this bus can require more than

two cycles for reads and writes depending on the peripheral’s structure.

The ’54x devices can have bus keepers connected to the data bus. Bus keepers ensure that the data bus does

not float. When bus keepers are enabled, the data bus maintains its previous level. Setting bit 1 of the bank

switching control register (BSCR) enables bus keepers and clearing bit 1 disables the bus keepers. A reset

automatically disables the bus keepers.

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