TMS320VC549 datasheet(75/111 Pages) TI

75 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port write

(IOSTRB = 0) [H = 0.5 tc(CO)] (see Figure 19)†

PARAMETER

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN

MAX

MIN

MAX

td(CLKL-A)

Delay time, address valid from CLKOUT low‡

td(CLKH-ISTRBL)

Delay time, IOSTRB low from CLKOUT high

–2

td(CLKH-D)IOW

Delay time, write data valid from CLKOUT high

H–5

H+10

H–5

H+8

td(CLKH-ISTRBH)

Delay time, IOSTRB high from CLKOUT high

– 2

–2

td(CLKL-RWL)

Delay time, R/W low from CLKOUT low

td(CLKL-RWH)

Delay time, R/W high from CLKOUT low

– 2

–2

th(A)IOW

Hold time, address valid from CLKOUT low‡

th(D)IOW

Hold time, write data after IOSTRB high

H–5

H+5

H–5

H+5

tsu(D)IOSTRBH

Setup time, write data before IOSTRB high

H–7

H–5

tsu(A)IOSTRBL

Setup time, address valid before IOSTRB low

H–5

H+5

H–5

H+5

† See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

‡ Address and IS timings are included in timings referenced as address.

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