поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

TMS320VC549 датащи(PDF) 68 Page - Texas Instruments

номер детали TMS320VC549
подробное описание детали  FIXED-POINT DIGITAL SIGNAL PROCESSORS
PDF  111 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC549 датащи(HTML) 68 Page - Texas Instruments

Back Button TMS320VC549 Datasheet HTML 64Page - Texas Instruments TMS320VC549 Datasheet HTML 65Page - Texas Instruments TMS320VC549 Datasheet HTML 66Page - Texas Instruments TMS320VC549 Datasheet HTML 67Page - Texas Instruments TMS320VC549 Datasheet HTML 68Page - Texas Instruments TMS320VC549 Datasheet HTML 69Page - Texas Instruments TMS320VC549 Datasheet HTML 70Page - Texas Instruments TMS320VC549 Datasheet HTML 71Page - Texas Instruments TMS320VC549 Datasheet HTML 72Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 68 / 111 page
background image
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
68
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface timing
switching characteristics over recommended operating conditions for a memory read
(MSTRB = 0)†‡ (see Figure 16)
PARAMETER
’LC542-40
’LC543-40
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
td(CLKL-A)
Delay time, address valid from
CLKOUT low§
0
5
0
5
0
5
0
5
ns
td(CLKH-A)
Delay time, address valid from
CLKOUT high (transition)¶
0
5
0
5
0
5
– 2
3
ns
td(CLKL-MSL)
Delay time, MSTRB low from CLKOUT
low
0
5
0
5
0
5
0
5
ns
td(CLKL-MSH)
Delay time, MSTRB high from
CLKOUT low
– 2
3
– 2
3
– 2
3
– 2
3
ns
th(CLKL-A)R
Hold time, address valid after CLKOUT
low§
0
5
0
5
0
5
0
5
ns
th(CLKH-A)R
Hold time, address valid after CLKOUT
high¶
0
5
0
5
0
5
– 2
3
ns
† Address, PS, and DS timings are all included in timings referenced as address.
‡ See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.
§ In the case of a memory read preceded by a memory read
¶ In the case of a memory read preceded by a memory write



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com