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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC549 датащи(PDF) 74 Page - Texas Instruments |
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TMS320VC549 датащи(HTML) 74 Page - Texas Instruments |
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74 / 111 page  TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 18) ’LC542-40 ’LC543-40 ’C54x-40 ’LC54x-40 ’LC54x-50 ’54x-66 UNIT MIN MAX MIN MAX MIN MAX ta(A)IO Access time, read data access from address valid 3H–12 3H–10 3H–10 ns ta(ISTRBL)IO Access time, read data access from IOSTRB low 2H–12 2H–10 2H–10 ns tsu(D)IOR Setup time, read data before CLKOUT high 7 5 5 ns th(D)IOR Hold time, read data after CLKOUT high 0 0 0 ns th(ISTRBH-D)R Hold time, read data after IOSTRB high 0 0 0 ns † Address and IS timings are included in timings referenced as address. ‡ See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance. IS R/W IOSTRB D[15:0] A[15:0] CLKOUT th(A)IOR td(CLKH-ISTRBH) th(D)IOR tsu(D)IOR ta(A)IO td(CLKH-ISTRBL) td(CLKL-A) ta(ISTRBL)IO th(ISTRBH-D)R Figure 18. Parallel I/O Port Read (IOSTRB = 0) |
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