TMS320VC549 datasheet(48/111 Pages) TI

48 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Table 13. ’54x Instruction Set Opcodes (Continued)

MNEMONIC SYNTAX

OPCODE

WORDS/

CYCLES†

DESCRIPTION

MNEMONIC SYNTAX

LSB

MSB

WORDS/

CYCLES†

DESCRIPTION

ARITHMETIC INSTRUCTIONS (CONTINUED)

MAS[R]

Xmem, Ymem, src [, dst ]

Multiply dual, subtract from ACC [round]

1/1

1011

1RSD

XXXX

YYYY

MASA

Smem [, B ]

Multiply operand by ACCA, subtract from ACCB

1/1

0011

IAAA

AAAA

MASA[R] T,

src [, dst ]

Multiply ACCA by T, subtract from ACC [round]

1/1

1111

01SD

1000

101R

MAX

dst

Accumulator maximum

1/1

1111

010D

1000

0110

MIN

dst

Accumulator minimum

1/1

1111

010D

1000

0111

MPY[R]

Smem, dst

Multiply TREG by operand, round if specified

1/1

0010

00RD

IAAA

AAAA

MPY

Xmem, Ymem, dst

Multiply dual data-memory operands

1/1

1010

010D

XXXX

YYYY

MPY

Smem, #lk, dst

Multiply operand by long-immediate operand

2/2

0110

001D

IAAA

AAAA

MPY #

lk, dst

Multiply TREG value by long-immediate operand

2/2

1111

000D

0110

MPYA

Smem

Multiply single data-memory operand by ACCA

1/1

0011

0001

IAAA

AAAA

MPYA

dst

Multiply TREG value by ACCA

1/1

1111

010D

1000

1100

MPYU

Smem, dst

Multiply unsigned

1/1

0010

010D

IAAA

AAAA

NEG

src [, dst ]

Negate accumulator

1/1

1111

01SD

1000

0100

NORM

src [, dst ]

Normalize

1/1

1111

01SD

1000

1111

POLY

Smem

Evaluate polynomial

1/1

0011

0110

IAAA

AAAA

RND

src [, dst ]

Round accumulator

1/1

1111

01SD

1001

1111

SAT

src

Saturate accumulator

1/1

1111

010S

1000

0011

SQDST

Xmem, Ymem

Square distance

1/1

1110

0010

XXXX

YYYY

SQUR

Smem, dst

Square single data-memory operand

1/1

0010

011D

IAAA

AAAA

SQUR A

, dst

Square ACCA high

1/1

1111

010D

1000

1101

SQURA

Smem, src

Square and accumulate

1/1

0011

100S

IAAA

AAAA

SQURS

Smem, src

Square and subtract

1/1

0011

101S

IAAA

AAAA

SUB

Smem, src

Subtract operand from accumulator

1/1

0000

100S

IAAA

AAAA

SUB

Smem, TS, src

Shift by TREG[5:0], then subtract from ACC

1/1

0000

110S

IAAA

AAAA

SUB

Smem, 16, src [, dst ]

Shift operand 16 bits, then subtract from ACC

1/1

0100

00SD

IAAA

AAAA

SUB

Smem [, SHIFT ], src [, dst ]

Shift operand, then subtract from ACC

(2-word opcode)

2/2

0110

0000

1111

11SD

IAAA

001S

AAAA

HIFT

SUB

Xmem, SHFT, src

Shift operand, then subtract from ACC

1/1

1001

001S

XXXX

SHFT

SUB

Xmem, Ymem, dst

Shift dual operands by 16, then subtract

1/1

1010

001D

XXXX

YYYY

SUB #

lk [, SHFT ], src [, dst ]

Shift long-immediate, then subtract from ACC

2/2

1111

00SD

0001

SHFT

SUB #

lk, 16, src [, dst ]

Shift long-immediate 16 bits, subtract from ACC

2/2

1111

00SD

0110

0001

SUB

src [, SHIFT ], [, dst ]

Subtract shifted ACC from ACC

1/1

1111

01SD

001S

HIFT

SUB

src, ASM [, dst ]

Subtract ACC shifted by ASM from ACC

1/1

1111

01SD

1000

0001

SUBB

Smem, src

Subtract from accumulator with borrow

1/1

0000

111D

IAAA

AAAA

SUBC

Smem, src

Subtract conditionally

1/1

0001

111S

IAAA

AAAA

SUBS

Smem, src

Subtract from ACC, sign-extension suppressed

1/1

0000

101S

IAAA

AAAA

† Values for words and cycles assume the use of DARAM for data. Add one word and one cycle when using long-offset indirect addressing or

absolute addressing with a single data-memory operand.

‡ Delayed Instruction

§ Condition true

¶ Condition false

instruction set summary (continued)

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