TMS320VC549 datasheet(96/111 Pages) TI

96 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

buffered serial port transmit timing of internal frame and internal clock

switching characteristics over recommended operating conditions for buffered serial port

transmit of internal frame and internal clock [H = 0.5tc(CO)] (see Figure 37)

PARAMETER

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN

MAX

MIN

MAX

tc(SCK)

Cycle time, serial port clock, internal clock

62H

td(BFSX)

Delay time, BFSX after BCLKX rising edge

(see Notes 3 and 4)

td(BDX)

Delay time, BDX valid after BCLKX rising edge

tdis(BDX)

Disable time, BDX after BCLKX rising edge

tdis(BDX)pcm

Disable time, PCM mode, BDX after BCLKX rising edge

ten(BDX)pcm

Enable time, PCM mode, BDX after BCLKX rising edge

th(BDX)

Hold time, BDX valid after BCLKX rising edge

tf(SCK)

Fall time, serial port clock

tr(SCK)

Rise time, serial port clock

tw(SCK)

Pulse duration, serial port clock low/high

H–4

NOTES:

3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined

depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.

4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.

8/10/12/16

BDX

BFSX

BCLKX

tc(SCK)

td(BFSX)

tdis(BDX)

tw(SCK)

th(BDX)

td(BDX)

tw(SCK)

tr(SCK)

tf(SCK)

Figure 37. Buffered Serial Port Transmit Timing of Internal Clocks and Internal Frames

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