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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC549 датащи(PDF) 65 Page - Texas Instruments |
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TMS320VC549 датащи(HTML) 65 Page - Texas Instruments |
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65 / 111 page  TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 65 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 divide-by-two/divide-by-four clock option – PLL disabled (continued) timing requirements for divide-by-two/divide-by-four clock option – PLL disabled (see Figure 14) ’C54x-40 ’LC54x-40 ’LC54x-50 ’54x-66 UNIT MIN MAX MIN MAX MIN MAX UNIT tc(CI) Cycle time, X2/CLKIN 20‡ † 20‡ † 20‡ † ns tf(CI) Fall time, X2/CLKIN 4 4 4 ns tr(CI) Rise time, X2/CLKIN 4 4 4 ns tw(CIL) Pulse duration, X2/CLKIN low 5 † 5 † 5 † ns tw(CIH) Pulse duration, X2/CLKIN high 5 † 5 † 5 † ns † This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies approaching 0 Hz. ‡ It is recommended that the PLL clocking option be used for maximum frequency operation. tr(CO) tf(CO) CLKOUT X2/CLKIN tw(COL) td(CIH-CO) tf(CI) tr(CI) tc(CO) tc(CI) tw(COH) tw(CIL) tw(CIH) Figure 14. External Divide-by-Two Clock Timing |
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