TMS320VC549 datasheet(32/111 Pages) TI

32 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

hardware-programmable PLL (continued)

Table 4. Clock Mode Configurations

MODE-SELECT PINS

CLOCK MODE

CLKMD1

CLKMD2

CLKMD3

OPTION 1†

OPTION 2†

PLL

× 3 with external source

PLL

× 5 with external source

PLL

× 2 with external source

PLL

× 4 with external source

PLL

× 3, internal oscillator enabled

PLL

× 5, internal oscillator enabled

PLL

× 1.5 with external source

PLL

× 4.5 with external source

Divide-by-two with external source

Stop mode‡

PLL

× 1 with external source

PLL

× 1 with external source

Divide-by-two, internal oscillator enabled

† Option: Option 1 or option 2 is selected when ordering the device.

‡ Stop mode: The function of the stop mode is equivalent to that of the power-down mode of IDLE3; however, the IDLE3 instruction is recommended

rather than stop mode to realize full power saving, since IDLE3 stops clocks synchronously and can be exited with an interrupt.

software-programmable PLL (’545A, ’546A, ’548, and ’549)

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides

various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can

be used to delay switching to PLL clocking mode of the device until lock is achieved.

Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:

D PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved

using the PLL circuitry.

D DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be

completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode

CLKMD register fields are shown in Figure 7 and described below. Note that upon reset, the CLKMD register

is initialized with a predetermined value dependent only upon the state of the CLKMD1 – CLKMD3 pins (see

Table 6).

Bit #

15–12

10–3

PLLMUL

PLLDIV

PLLCOUNT

PLLON/OFF

PLLNDIV

PLLSTATUS

R/W†

R/W

R = read, W = write

† When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are

indeterminate.

Figure 7. Clock Mode Control Register (CLKMD)

TMS320VC549 датащи(PDF) 32 Page - Texas Instruments

TMS320VC549 датащи(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL