TMS320VC549 datasheet(79/111 Pages) TI

79 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

ready timing for externally generated wait states

timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 21, Figure 22,

Figure 23, and Figure 24)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tsu(RDY)

Setup time, READY before CLKOUT low

th(RDY)

Hold time, READY after CLKOUT low

tv(RDY)MSTRB

Valid time, READY after MSTRB low‡

4H – 15

4H – 12

4H–10

th(RDY)MSTRB

Hold time, READY after MSTRB low‡

tv(RDY)IOSTRB

Valid time, READY after IOSTRB low‡

5H – 15

5H – 12

5H–10

th(RDY)IOSTRB

Hold time, READY after IOSTRB low‡

tv(MSCL)

Valid time, MSC low after CLKOUT low

tv(MSCH)

Valid time, MSC high after CLKOUT low

–2

† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by

READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.

‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.

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