SH7713 datasheet(132/904 Pages) RENESAS

132 / 904 page

Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 92 of 860

REJ09B0288-0150

BRA, BSR, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP

 Repeat control instructions

SETRC, LDRS, LDRE, LDRC

 Load instructions for SR, RS, and RE registers

LCD Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS

Note:

A branch instruction without delay (BT, BF, TRAPA) can be placed as a repeat end

instruction. A delay stop of a delayed branch instruction can also be placed as a repeat end

instruction. In this case, the RC[11:0] value is decremented by 1 regardless of branch

occurrence. If no branch occurs, a control returns to a repeat start instruction. If a branch

occurs, a control is passed to a branch destination.

3. Repeat counter and repeat control

The CPU always execute a program with comparing the repeat end register (RE) and the (PC –

4) (current instruction address). If the (PC – 4) [31:1] matches the RE [31:1] while bit 0 of RE

initiated.

 If RC ≥ 2, a control is passed to a repeat start instruction after a repeat end instruction has

been executed. The RC is decremented by 1 at the completion of the repeat end instruction.

 If RC == 1, the RC is decremented to 0 at the completion of the repeat end instruction and

a control is passed to the subsequent instruction.

 If RC == 0, the repeat control function is not initiated even if a repeat detection instruction

is executed. The repeat loop is executed once as normal instructions and a control is not be

passed to a repeat start instruction even if a repeat end instruction is executed.

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