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SH7713 датащи(PDF) 35 Page - Renesas Technology Corp |
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SH7713 датащи(HTML) 35 Page - Renesas Technology Corp |
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35 / 904 page ![]() Rev.1.50 Aug. 30, 2006 Page xxxv of xl Tables Section 1 Overview Table 1.1 Pin Assigument ....................................................................................................... 10 Table 1.2 Pin Functions .......................................................................................................... 19 Section 2 CPU Table 2.1 Logical Address Space............................................................................................ 30 Table 2.2 Register Initial Values............................................................................................. 33 Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions......................... 45 Table 2.4 CPU Instruction Formats ........................................................................................ 49 Table 2.5 CPU Instruction Types............................................................................................ 52 Table 2.6 Data Transfer Instructions....................................................................................... 56 Table 2.7 Arithmetic Operation Instructions .......................................................................... 58 Table 2.8 Logic Operation Instructions .................................................................................. 60 Table 2.9 Shift Instructions..................................................................................................... 61 Table 2.10 Branch Instructions ................................................................................................. 62 Table 2.11 System Control Instructions.................................................................................... 63 Table 2.12 Operation Code Map............................................................................................... 66 Section 3 DSP Operating Unit Table 3.1 Logical Address Space............................................................................................ 73 Table 3.2 Operation of SR Bits in Each Processing Mode ..................................................... 76 Table 3.3 RS and RE Setting Rule.......................................................................................... 82 Table 3.4 Repeat Control Instructions .................................................................................... 82 Table 3.5 Repeat Control Macros ........................................................................................... 83 Table 3.6 DSP Mode Extended System Control Instructions ................................................. 84 Table 3.7 PC Value during Repeat Control (When RC[11:0] ≥ 2) .........................................87 Table 3.8 Extended Repeat Control Instructions .................................................................... 91 Table 3.9 Extended System Control Instructions in DSP Mode ............................................. 96 Table 3.10 Overview of Data Transfer Instructions.................................................................. 99 Table 3.11 Modulo Addressing Control Instructions.............................................................. 101 Table 3.12 Double Data Transfer Instruction Formats ........................................................... 104 Table 3.13 Single Data Transfer Instruction Formats ............................................................. 105 Table 3.14 Destination Register in DSP Instructions.............................................................. 107 Table 3.15 Source Register in DSP Operations ...................................................................... 108 Table 3.16 DSR Register Bits................................................................................................. 109 Table 3.17 DSP Operation Instruction Formats...................................................................... 112 Table 3.18 Correspondence between DSP Instruction Operands and Registers ..................... 112 Table 3.19 DC Bit Update Definitions.................................................................................... 114 |
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