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SH7713 датащи(PDF) 95 Page - Renesas Technology Corp

номер детали SH7713
подробное описание детали  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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SH7713 датащи(HTML) 95 Page - Renesas Technology Corp

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Section 2 CPU
Rev.1.50 Aug. 30, 2006 Page 55 of 860
REJ09B0288-0150
Instruction
Instruction Code
Operation
Privilege
Execution
States
T Bit
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
OP:
Operation code
Sz:
Size
SRC:
Source
DEST: Destination
Rm:
Source register
Rn:
Destination register
imm: Immediate data
disp: Displacement
Indicated in MSB
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
.........
1111: R15
iiii:
Immediate data
dddd:
Displacement*
2
Indicates summary of
operation.
Explanation of Symbols
→, ←: Transfer direction
(xx):
Memory operand
M/Q/T: Flag bits in SR
&:
Logical AND of each bit
|:
Logical OR of each bit
^:
Exclusive logical OR of
each bit
~:
Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Indicates a
privileged
instruction.
Value
when no
wait states
are
inserted*
1
Value of T
bit after
instruction
is
executed
Explanatio
n of
Symbols
—: No
change
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
a.
When there is a conflict between an instruction fetch and a data access
b.
When the destination register of a load instruction (memory
→ register) is also used
by the following instruction
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.



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