SH7713 datasheet(20/904 Pages) RENESAS

20 / 904 page

Rev.1.50 Aug. 30, 2006 Page xx of xl

16.3.5 Serial Mode Register (SCSMR)............................................................................ 537

16.3.6 Serial Control Register (SCSCR).......................................................................... 541

16.3.7 Serial Status Register (SCFSR) ............................................................................ 545

16.3.8 Bit Rate Register (SCBRR) .................................................................................. 553

16.3.9 FIFO Control Register (SCFCR) .......................................................................... 554

16.3.10 FIFO Data Count Register (SCFDR) .................................................................... 556

16.3.11 Line Status Register (SCLSR) .............................................................................. 558

16.4

Operation ........................................................................................................................... 559

16.4.1 Overview .............................................................................................................. 559

16.4.2 Serial Operation in Asynchronous Mode.............................................................. 561

16.4.3 Serial Operation in Clock Synchronous Mode ..................................................... 572

16.5

SCIF Interrupt Sources and DMAC................................................................................... 582

16.6

Usage Notes ....................................................................................................................... 583

Section 17 Serial I/O with FIFO (SIOF) ........................................................... 587

17.1

Features.............................................................................................................................. 587

17.1.1 Block Diagram...................................................................................................... 588

17.2

Input/Output Pins...............................................................................................................589

17.3

Register Descriptions ......................................................................................................... 590

17.3.1 SIOF Mode Register (SIMDR)............................................................................. 591

17.3.2 Serial Clock Select Register (SISCR)................................................................... 593

17.3.3 Serial Transmit Data Assign Register (SITDAR)................................................. 594

17.3.4 Serial Receive Data Assign Register (SIRDAR) .................................................. 595

17.3.5 Serial Control Data Assign Register (SICDAR)................................................... 596

17.3.6 SIOF Control Register (SICTR) ........................................................................... 598

17.3.7 SIOF FIFO Control Register (SIFCTR)................................................................ 601

17.3.8 SIOF Status Register (SISTR) .............................................................................. 603

17.3.9 SIOF Interrupt Enable Register (SIIER)............................................................... 607

17.3.10 Serial Transmit Data Register (SITDR)................................................................ 609

17.3.11 Serial Receive Data Register (SIRDR) ................................................................. 610

17.3.12 Serial Transmit Control Data Register (SITCR)................................................... 611

17.3.13 Serial Receive Control Data Register (SIRCR) .................................................... 612

17.4

Operation ........................................................................................................................... 613

17.4.1 Serial Clocks......................................................................................................... 613

17.4.2 Serial Timing ........................................................................................................ 614

17.4.3 Transfer Data Format............................................................................................ 616

17.4.4 Register Allocation of Transfer Data .................................................................... 617

17.4.5 Control Data Interface .......................................................................................... 620

17.4.6 FIFO...................................................................................................................... 621

17.4.7 Transmission and Reception Procedures .............................................................. 623

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