SH7713 datasheet(26/904 Pages) RENESAS

26 / 904 page

Rev.1.50 Aug. 30, 2006 Page xxvi of xl

Section 4 Exception Handling

Figure 4.1 Register Bit Configuration ........................................................................................ 156

Section 5 Memory Management Unit (MMU)

Figure 5.1 MMU Functions ........................................................................................................ 183

Figure 5.2 Virtual Address Space (MMUCR.AT = 1)................................................................ 185

Figure 5.3 Virtual Address Space (MMUCR.AT = 0)................................................................ 186

Figure 5.4 P4 Area...................................................................................................................... 187

Figure 5.5 External Memory Space ............................................................................................ 188

Figure 5.6 Overall Configuration of the TLB............................................................................. 193

Figure 5.7 Virtual Address and TLB Structure........................................................................... 194

Figure 5.8 TLB Indexing (IX = 1) ..............................................................................................195

Figure 5.9 TLB Indexing (IX = 0) ..............................................................................................196

Figure 5.10 Objects of Address Comparison.............................................................................. 197

Figure 5.11 Operation of LDTLB Instruction............................................................................. 202

Figure 5.12 Synonym Problem (32-kbyte Cache) ...................................................................... 204

Figure 5.13 MMU Exception Generation Flowchart .................................................................. 210

Figure 5.14 Specifying Address and Data for Memory-Mapped TLB Access........................... 212

Section 6 Cache

Figure 6.1 Cache Structure ......................................................................................................... 215

Figure 6.2 Cache Search Scheme ............................................................................................... 223

Figure 6.3 Write-Back Buffer Configuration.............................................................................. 225

Figure 6.4 Specifying Address and Data for Memory-Mapped Cache Access

(16 kbytes mode)...................................................................................................... 228

Figure 6.5 Specifying Address and Data for Memory-Mapped Cache Access

(32 kbytes mode)...................................................................................................... 229

Section 8 Interrupt Controller (INTC)

Figure 8.1 Block Diagram of INTC............................................................................................ 236

Figure 8.2 Example of IRL Interrupt Connection....................................................................... 239

Figure 8.3 Interrupt Operation Flowchart................................................................................... 261

Section 9 User Break Controller

Figure 9.1 Block Diagram of User Break Controller.................................................................. 265

Section 10 Power-Down Modes

Figure 10.1 Canceling Standby Mode with STBCR.STBY........................................................ 305

Figure 10.2 STATUS Output at Power-On Reset....................................................................... 306

Figure 10.3 STATUS Output at Manual Reset........................................................................... 307

Figure 10.4 STATUS Output when Software Standby Mode is Canceled by Interrupt ............. 307

Figure 10.5 STATUS Output when Software Standby Mode is Canceled by

Power-on Reset ....................................................................................................... 308

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