SH7713 datasheet(37/904 Pages) RENESAS

37 / 904 page

Rev.1.50 Aug. 30, 2006 Page xxxvii of xl

Section 7 X/Y Memory

Table 7.1

X/Y Memory Logical Addresses .......................................................................... 231

Table 7.2

MMU and Cache Settings..................................................................................... 234

Section 8 Interrupt Controller (INTC)

Table 8.1

Pin Configuration.................................................................................................. 237

Table 8.2

Interrupt Exception Handling Sources and Priority (IRQ Mode) ......................... 240

Table 8.3

Interrupt Exception Handling Sources and Priority (IRL Mode).......................... 243

Table 8.4

Interrupt Level and INTEVT Code....................................................................... 245

Table 8.5

Interrupt Sources and IPRA to IPRI ..................................................................... 247

Section 9 User Break Controller

Table 9.1

Specifying Break Address Register ...................................................................... 269

Table 9.2

Specifying Break Data Register............................................................................ 271

Table 9.3

Data Access Cycle Addresses and Operand Size Comparison Conditions........... 284

Section 10 Power-Down Modes

Table 10.1

States of Power-Down Modes .............................................................................. 296

Table 10.2

Pin Configuration.................................................................................................. 298

Table 10.3

Section 11 On-Chip Oscillation Circuits

Table 11.1

Pin Configuration.................................................................................................. 315

Table 11.2

Clock Operating Modes ........................................................................................ 315

Table 11.3

Possible Combination of Clock Mode and FRQCR Values.................................. 317

Section 12 Bus State Controller (BSC)

Table 12.1

Pin Configuration.................................................................................................. 334

Table 12.2

Address Space Map 1 (CMNCR.MAP = 0).......................................................... 338

Table 12.3

Address Space Map 2 (CMNCR.MAP = 1).......................................................... 339

Table 12.4

Correspondence between External Pins (MD3 and MD4), Memory Type of

CS0, and Memory Bus Width............................................................................... 340

Table 12.5

Correspondence between External Pin (MD5) and Endians ................................. 340

Table 12.6

32-Bit External Device/Big Endian Access and Data Alignment......................... 384

Table 12.7

16-Bit External Device/Big Endian Access and Data Alignment......................... 385

Table 12.8

8-Bit External Device/Big Endian Access and Data Alignment........................... 386

Table 12.9

32-Bit External Device/Little Endian Access and Data Alignment ...................... 387

Table 12.10

16-Bit External Device/Little Endian Access and Data Alignment .................. 388

Table 12.11

8-Bit External Device/Little Endian Access and Data Alignment .................... 389

Table 12.12

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and

Address Multiplex Output (1)-1........................................................................ 402

Table 12.12

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and

Address Multiplex Output (1)-2........................................................................ 404

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