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SH7713 датащи(PDF) 62 Page - Renesas Technology Corp

номер детали SH7713
подробное описание детали  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 датащи(HTML) 62 Page - Renesas Technology Corp

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Section 1 Overview and Pin Function
Rev.1.50 Aug. 30, 2006 Page 22 of 860
REJ09B0288-0150
Classification
Symbol
I/O
Name
Function
WE0(BE0)
O
Byte write
Indicates that bits 7 to 0 of the data
in the external memory or device are
being written.
RAS
O
RAS
Connects RAS pin during access to
the SDRAM.
CAS
O
CAS
Connects CAS pin during access to
the SDRAM.
CKE
O
CK enable
Connects CKE pin during access to
the SDRAM.
IOIS16
I
16-bit I/O
selection
Indicates 16-bit I/O for PCMCIA.
DQMUU
O
DQM
Selects D31 to D24 during access to
the SDRAM.
DQMUL
O
DQM
Selects D23 to D16 during access to
the SDRAM.
DQMLU
O
DQM
Selects D15 to D8 during access to
the SDRAM.
DQMLL
O
DQM
Selects D7 to D0 during access to
the SDRAM.
REFOUT
O
Refresh request
output
Outputs the refresh request in
master mode or bus release.
Bus control
WAIT
I
Wait
Inserts a wait cycle into the bus
cycles during access to the external
space.
DREQ0,
DREQ1
I
DMA-transfer
request
Input pin for external requests for
DMA transfer.
DACK0,
DACK1
O
DMA-transfer
request accept
Output pin for request acceptance,
in response to external requests for
DMA transfer.
Direct memory
access controller
(DMAC)
TEND0,
TEND1
O
DMA-transfer
end output
Output pin for DMA transfer end
signal.



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