SH7713 datasheet(41/904 Pages) RENESAS

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Section 1 Overview and Pin Function

Rev.1.50 Aug. 30, 2006 Page 1 of 860

REJ09B0288-0150

Section 1 Overview and Pin Function

This LSI is a 32-bit reduced instruction set computer (RISC) microprocessor that is built on the

SuperH architecture.

Its core is a RISC-type CPU with a Digital Signal Processor (DSP) as a functional extension. A

single chip microprocessor integrates peripheral functions required for building an Ethernet

system.

The LSI comprises one channel of Ethernet controller. It includes a media access controller

(MAC) and a media independent interface (MII) standard unit that conforms to the IEE802.3u

standard and provides 10/100 Mbps LAN connection.

The LSI has a large capacity (32-kbyte) cache memory, 16-kbyte on-chip X/Y memory, and an

interrupt controller for system configuration to enable flexible system design. It supports high-

speed data transfer using an on-chip direct memory access controller (DMAC). Its external

memory access support provides direct connection to various types of memory.

The strong on-chip power saving function reduces power consumption even during high-speed

operation.

1.1

Features

The features of this LSI are shown below.

CPU:

• Original Renesas-Technology SuperH architecture

• Compatible with SH-1, SH-2, and SH-3 at object code level

• 32-bit internal data bus

• Various groups of built-in registers

General registers: Sixteen 32-bit registers (including eight 32-bit bank registers)

Control registers: Five 32-bit registers

System registers: Four 32-bit registers

• Supports RISC-type instruction set

Instruction length: 16-bit fixed length for improved code efficiency

Load/store architecture

Delayed branch instructions

Instruction set based on C language

• Instruction execution time: one instruction/cycle for basic instructions

• Logical address space: 4 Gbytes

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