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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7713 датащи(PDF) 93 Page - Renesas Technology Corp |
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SH7713 датащи(HTML) 93 Page - Renesas Technology Corp |
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93 / 904 page  Section 2 CPU Rev.1.50 Aug. 30, 2006 Page 53 of 860 REJ09B0288-0150 Type Kinds of Instruction Op Code Function Number of Instructions 21 MAC Multiply-and-accumulate, double- precision multiply-and-accumulate 33 MUL Double-precision multiplication (32 × 32 bits) MULS Signed multiplication (16 × 16 bits) MULU Unsigned multiplication (16 × 16 bits) NEG Sign inversion NEGC Sign inversion with borrow SUB Binary subtraction SUBC Binary subtraction with carry Arithmetic operation instructions SUBV Binary subtraction with underflow 6 AND Logical AND 14 NOT Bit inversion OR Logical OR TAS Memory test and bit setting TST Logical AND and T bit setting Logic operation instructions XOR Exclusive logical OR 12 ROTL 1-bit left shift 16 ROTR 1-bit right shift ROTCL 1-bit left shift with T bit ROTCR 1-bit right shift with T bit SHAL Arithmetic 1-bit left shift SHAR Arithmetic 1-bit right shift SHLL Logical 1-bit left shift SHLLn Logical n-bit left shift SHLR Logical 1-bit right shift SHLRn Logical n-bit right shift SHAD Arithmetic dynamic shift Shift instructions SHLD Logical dynamic shift |
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