SH7713 datasheet(18/904 Pages) RENESAS

18 / 904 page

Rev.1.50 Aug. 30, 2006 Page xviii of xl

12.5.12 Others.................................................................................................................... 456

Section 13 Direct Memory Access Controller (DMAC) ................................... 459

13.1

Features.............................................................................................................................. 459

13.2

Input/Output Pins...............................................................................................................461

13.3

Register Descriptions ......................................................................................................... 462

13.3.1 DMA Source Address Register (SAR) ................................................................. 463

13.3.2 DMA Destination Address Register (DAR) ......................................................... 463

13.3.3 DMA Transfer Count Register (DMATCR) ......................................................... 464

13.3.4 DMA Channel Control Register (CHCR)............................................................. 464

13.3.5 DMA Operation Register (DMAOR) ................................................................... 469

13.3.6 DMA Extension Resource Selector 0 to 2 (DMARS0 to DMARS2) ................... 471

13.4

Operation ........................................................................................................................... 474

13.4.1 DMA Transfer Flow ............................................................................................. 474

13.4.2 DMA Transfer Requests ....................................................................................... 477

13.4.3 Channel Priority.................................................................................................... 479

13.4.4 DMA Transfer Types............................................................................................ 482

13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 489

13.5

Usage Note......................................................................................................................... 493

Section 14 Timer Unit (TMU)........................................................................... 495

14.1

Features.............................................................................................................................. 495

14.1.1 Block Diagram...................................................................................................... 495

14.2

Register Descriptions ......................................................................................................... 497

14.2.1 Timer Start Register (TSTR) ................................................................................ 497

14.2.2 Timer Control Registers (TCR) ............................................................................ 498

14.2.3 Timer Constant Registers (TCOR) ....................................................................... 499

14.2.4 Timer Counters (TCNT) ....................................................................................... 499

14.3

TMU Operation.................................................................................................................. 500

14.3.1 Counter Operation ................................................................................................ 500

14.4

Interrupts............................................................................................................................ 503

14.4.1 Status Flag Set Timing.......................................................................................... 503

14.4.2 Status Flag Clear Timing ...................................................................................... 503

14.4.3 Interrupt Sources and Priorities ............................................................................ 504

14.5

Usage Notes ....................................................................................................................... 504

14.5.1 Writing to Registers .............................................................................................. 504

14.5.2 Reading Registers ................................................................................................. 504

Section 15 Realtime Clock (RTC)..................................................................... 505

15.1

Feature ............................................................................................................................... 505

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