M16CSLASH1N datasheet(202/238 Pages) RENESAS

202 / 238 page

Rev.1.00

Oct 20, 2004

page 190 of 222

M16C/1N Group

19. Flash Memory Version

REJ09B0007-0100Z

Write ’xxD016’ to the uppermost

block address (Note 1)

Write the command code ’xx2016’

(Note 1)

Start

Block erase completed

YES

FMR00=1?

Full status check (Note 2, 3)

Note 1: Write the command code and data at even number.

Note 2: See Figure 19.12 Full status check flowchart, handling each error generated.

Note 3: When the erase error occurred, repeat the operation executing the clear status register command

and then the block erase command in succession at least 3 times until the error is eliminated.

Figure 19.10 Block erase flowchart (when not using the erasure suspend feature)

(5) Block erase

Write 'xx2016' in the first bus cycle and write 'xxD016' to the uppermost address of a block (even

address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.

Check the FMR0 register's FMR00 bit to see if auto erasing has finished.

The FMR00 bit is "0" during auto erasing and set to "1" when auto erasing is completed.

In EW0 mode, when using the erasure suspend feature, confirm the FMR4 register's FMR46 bit

whether it has shifted to erasure suspend.

The FMR46 bit is "0" during auto erasing and is set to "1" when auto erasing is suspended (shift to

erasure suspend).

Check the FMR0 register's FMR07 bit after auto erasing has finished, and the result of auto erasing

can be known (refer to 19.5.6 Full Status Check).

Also, block 0 and 1 do not accept the block erase command while the FMR0 register's FMR02 bit is set

to "0" (Inhibit rewriting.)

Figure 19.10 shows an example of a block erase flowchart when not using the erasure suspend

feature and Figure 19.11 shows an example of a block erase flowchart when using the erasure sus-

pend feature.

In EW1 mode, do not execute this command on any address at which the rewrite control program is located.

In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing

starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to "0" at

the same time auto erasing starts, and set back to "1" when auto erasing finishes. In this case, the

microcomputer remains in read status register mode until the read array command is written next. In

addition, when the erase error occurred, repeat the operation executing the clear status register com-

mand and then the block erase command in succession at least 3 times until the error is eliminated.

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