M16CSLASH1N datasheet(45/238 Pages) RENESAS

45 / 238 page

Rev.1.00

Oct 20, 2004

page 33 of 222

M16C/1N Group

6. Clock Generation Circuit

REJ09B0007-0100Z

States

Port

Retains status before stop mode

6.5.3 Stop Mode

Writing "1" to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the micro-

computer enters stop mode. In stop mode, the content of the internal RAM is retained provided that

VCC remains above 2V.

Because the oscillation of BCLK, f1 to f32, fc, fc32, fAD and fCAN0 stop in stop mode, peripheral func-

tions such as the A/D converter and watchdog timer do not function. However, timer X operate pro-

vided that the event counter mode is set to an external pulse, and UART0 and UART1 function pro-

vided an external clock is selected. Table 6.4 lists the status of the ports in stop mode.

Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop

mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not

used to cancel must have been changed to 0 before shifting to stop mode. If returning by an interrupt,

that interrupt routine is executed. If only a hardware reset is used to cancel stop mode, change the

priority level of all interrupt to 0, then shift to stop mode.

When shifting from high-speed/medium-speed mode to stop mode or at a reset, the main clock divi-

sion select bit 0 (bit 6 at address 000616) is set to "1". When shifting from low-speed/low power dissi-

pation mode to stop mode, the value before stop mode is retained.

Stop mode must not be use while operating in on-chip oscillator mode.

6.5.2 Wait Mode

When a WAIT instruction is executed, BCLK stops and the microcomputer enters wait mode. In this

mode, oscillation continues but BCLKand watchdog timer stop. Writing "1" to the WAIT peripheral

function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal

peripheral functions, allowing power dissipation to be reduced. Table 6.3 lists the status of the ports in

wait mode.

Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode,

the microcomputer restarts using as BCLK, the clock that had been selected when the WAIT instruc-

tion was executed.

Table 6.4 Port status during stop mode

Table 6.3 Port status during wait mode

States

Port

Retains status before wait mode

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