M16CSLASH1N datasheet(65/238 Pages) RENESAS

65 / 238 page

Rev.1.00

Oct 20, 2004

page 53 of 222

M16C/1N Group

10. Interrupt

REJ09B0007-0100Z

10.1.5.4 Rewrite the Interrupt Control Register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request

for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear T1IC int. priority level and int. request bit.

NOP

;

NOP

FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear T1IC int. priority level and int. request bit.

MOV.W

MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC

FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear T1IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is

to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to

effects of the instruction queue.

When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled,

the interrupt request bit is not set sometimes even if the interrupt request for that register has been

generated. This will depend on the instruction. If this creates problems, use the below instructions

to change the register.

Instructions : AND, OR, BCLR, BSET

Changing the interrupt request bit

When attempting to clear the interrupt request bit of an interrupt control register, the interrupt

request bit is not cleared sometimes. This will depend on the instruction. If this creates problems,

use the below instructions to change the register.

Instructions : MOV

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